mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 70

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

MG82FE(L)308/316
MEGAWIN
Preliminary, v 0.04
MAKE YOU WIN
16. Power Management
The MG82FE(L)308/316 supports one power monitor module, Brown-Out Detector, and two power-reducing
modes: Idle and Power-down. These modes are accessed through the PCON0 and PCON1 register.
16.1. Power Saving Mode
16.1.1. Idle Mode
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is preserved
in its entirety, including the RAM, stack pointer, program counter, program status word, and accumulator. The
Port pins hold the logical states they had at the time that Idle was activated. Idle mode leaves the peripherals
running in order to allow them to wake up the CPU when an interrupt is generated. Timer 0, Timer 1, Timer 2,
PWM Timer and the UART will continue to function during Idle mode. The analog comparator and WDT are
conditional enabled during Idle mode to wake up CPU. Any enabled interrupt source or reset may terminate Idle
mode. When exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and following RETI,
the next instruction to be executed will be the one following the instruction that put the device into Idle. There is
another Idle existing mechanism by enabled wakeup GPIOs that don’t builds interrupt capability.
The channel inputs of analog comparator should be set to “output 0” or “quasi-bidirectional” when comparator is
disabled in idle mode or power-down mode.
16.1.2. Power-down Mode
Setting the PD bit in PCON enters Power-down mode. Power-down mode stops the oscillator and powers down
the Flash memory in order to minimize power consumption. Only the power-on circuitry will continue to draw
power during Power-down. During Power-down the power supply voltage may be reduced to the RAM keep-alive
voltage. The RAM contents will be retained; however, the SFR contents are not guaranteed once VDD has been
reduced. Power-down may be exited by external reset, power-on reset, enabled external interrupts, enabled
wakeup GPIOs or enabled Non-Stop WDT.
The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 μs until after one of
the following conditions has occurred: Start of code execution (after any type of reset), or Exit from power-down
mode.
16.1.3. Interrupt Recovery from Power-down
Six external interrupts may be configured to terminate Power-down mode. External interrupts nINT0 (P3.2),
nINT1 (P3.3), nINT2 (P4.3), nINT3 (P4.2), nINT4 (P5.0) and nINT5 (P5.1) may be used to exit Power-down. To
wake up by external interrupt nINT0, nINT1, nINT2, nINT3, nINT4 or nINT5, the interrupt must be enabled and
configured for level-sensitive operation.
When terminating Power-down by an interrupt, the wake up period is internally timed. At the falling edge on the
interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal
clock will not be allowed to propagate and the CPU will not resume execution until after the timer has reached
internal counter full. After the timeout period, the interrupt service routine will begin. To prevent the interrupt from
re-triggering, the ISR should disable the interrupt before returning. The interrupt pin should be held low until the
device has timed out and begun executing.
16.1.4. Reset Recovery from Power-down
Wakeup from Power-down through an external reset is similar to the interrupt. At the rising edge of RST,
Power-down is exited, the oscillator is restarted, and an internal timer begins counting. The internal clock will not
be allowed to propagate to the CPU until after the timer has reached internal counter full. The RST pin must be
held high for longer than the timeout period to ensure that the device is reset properly. The device will begin
executing once RST is brought low.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
70/84