mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 75
mg82fel308
Manufacturer Part Number
mg82fel308
Description
A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
Manufacturer
Megawin Technology
Datasheet
1.MG82FEL308.pdf
(84 pages)
- Current page: 75 of 84
- Download datasheet (2Mb)
MG82FE(L)308/316
MEGAWIN
Preliminary, v 0.04
MAKE YOU WIN
Bit 3~0 : Reserved
ISP Description in more detail
MG82FE(L)308/316 does not make use of idle-mode to perform ISP operation. Instead, it creates CPU wait-state
to release flash memory for ISP control circuit use. Once ISP run over, CPU will be waken-up and advanced to
the instruction which follows the previous instruction that invokes ISP activity. During ISP operation, interrupt
service is also blocked until ISP run over.
ISP control circuit has a built-in timer for timing sequence control. It is referred from OSC frequency and defined
by CKCON2.XCKS[4:0] to get the accuracy erase/program timing.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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