mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 42

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mg82fel308

Manufacturer Part Number
mg82fel308
Description
A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
Manufacturer
Megawin Technology
Datasheet
12.1.6. Timer0/1 Register
TMOD: Timer/Counter Mode Control Register
SFR Address
SFR Page
| ----------------------- Timer1 ------------------------- | --------------------------Timer0 ------------------------ |
Bit 7/3: Gate, Gating control for Timer1/0.
0: Disable gating control for Timer1/0.
1: Enable gating control for Timer1/0. When set, Timer1/0 or Counter1/0 is enabled only when /INT1 or /INT0 pin
Bit 6/2: C/T, Timer for Counter function selector.
0: Clear for Timer operation, input from internal system clock.
1: Set for Counter operation, input form T1 input pin.
Bit 5~4/1~0: Operating mode selection.
M1
TCON: Timer/Counter Control Register
SFR Address
SFR Page
Bit 7: TF1, Timer 1 overflow flag.
0: Cleared by hardware when the processor vectors to the interrupt routine, or cleared by software.
1: Set by hardware on Timer/Counter 1 overflow, or set by software.
Bit 6: TR1, Timer 1 Run control bit.
0: Cleared by software to turn Timer/Counter 1 off.
1: Set by software to turn Timer/Counter 1 on.
Bit 5: TF0, Timer 0 overflow flag.
0: Cleared by hardware when the processor vectors to the interrupt routine, or cleared by software.
1: Set by hardware on Timer/Counter 0 overflow, or set by software.
Bit 4: TR0, Timer 0 Run control bit.
0: Cleared by software to turn Timer/Counter 0 off.
1: Set by software to turn Timer/Counter 0 on.
Bit 3: IE1, Interrupt 1 Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 1 edge is detected (transmitted or level-activated).
Bit 2: IT1: Interrupt 1 Type control bit.
0: Cleared by software to specify low level triggered external interrupt 1.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
42/84
0
0
1
1
1
is high and TR1 or TR0 control bit is set.
GATE
TF1
R/W
R/W
7
7
M0
0
1
0
1 (Timer0)
1 (Timer1)
MEGAWIN
MAKE YOU WIN
= 0x89
= All
= 0x88
= All
TR1
C/T
R/W
R/W
6
6
13-bit timer/counter for Timer0 and Timer1
16-bit timer/counter for Timer0 and Timer1
8-bit timer/counter with automatic reload for Timer0 and Timer1
TL0 is 8-bit timer/counter, TH0 is locked into 8-bit timer
Timer/Counter1 Stopped
Operating Mode
TF0
R/W
R/W
M1
5
5
TR0
R/W
R/W
M0
4
4
Reset Value = 0000-0000
Reset Value = 0000-0000
GATE
R/W
IE1
R/W
3
3
C/T
R/W
R/W
IT1
2
2
MG82FE(L)308/316
R/W
IE0
R/W
M1
1
1
Preliminary, v 0.04
R/W
R/W
M0
IT0
0
0

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