mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 60

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

13.5. Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications as shown in Figure 13-8. In these
two modes, 9 data bits are received. The 9th bit goes into RB8. Then comes a stop bit. The port can be
programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8=1. This
feature is enabled by setting bit SM2 (in SCON register). A way to use this feature in multiprocessor systems is
as follows:
When the master processor wants to transmit a block of data to one of several slaves, it first sends out an
address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an
address byte and 0 in a data byte. With SM2=1, no slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can examine the received byte and check if it is being
addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming.
The slaves that weren’t being addressed leave their SM2 set and go on about their business, ignoring the coming
data bytes.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1
reception, if SM2=1, the receive interrupt will not be activated unless a valid stop bit is received.
Figure 13-8 UART Multiprocessor Communications
13.6. Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial
bit stream by using hardware to make the comparisons. This feature saves a great deal of firmware overhead by
eliminating the need for the firmware to examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON.
In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the
received byte contains either the “Given” address or the “Broadcast” address. The 9-bit mode requires that the
9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address
recognition is shown in Figure 13-9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is
enabled and the information received has a valid stop bit following the 8 address bits and the information is eith
a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more
slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the
Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN.
SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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Slave 3
RX
TX
Slave 2
RX
TX
Slave 1
RX
TX
RX
Master
TX
VCC
R
Pull-up
MG82FE(L)308/316
Preliminary, v 0.04
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