mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 71

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

It should be noted that when idle is terminated by a hardware reset, the device normally resumes program
execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To
eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a port pin or to external memory.
16.1.5. GPIO wakeup Recovery from Power-down
The GPIOs of MG82FE(L)308/316, P1.7 ~ P1.0 and general ports (indexed by GPWKS[1:0]) have wakeup CPU
capability that are enabled by individual control bit in P1WKPE and GPWKPE. If the interrupt is disabled on
P3.2/nINT0, P3.3/nINT1, P5.0/nINT4 or P5.1/nINT5, P3.2, P3.3, P5.0 or P5.1 still have the wakeup function from
the GPWKPE control. But P4.2/nINT3 and P4.3/nINT2 can wakeup CPU only when the respective interrupt is
enabled.
Wakeup from Power-down through an enabled wakeup GPIO is similar to the interrupt. At the falling edge of
enabled wakeup GPIO, Power-down is exited, the oscillator is restarted, and an internal timer begins counting.
The internal clock will not be allowed to propagate to the CPU until after the timer has reached internal counter
full. After the timeout period, there is no any interrupt and CPU will execute the following command after last
power-down instruction. That is, the enabled wakeup GPIOs will only have the capability to wakeup CPU without
any interrupt function.
The enabled wakeup GPIOs also have the wakeup function form Idle mode. It will resume the CPU execute the
instruction following last halt CPU command, set IDLE instruction.
16.2. Brown-Out Detector
16.3. Power Control Register
PCON0: Power Control Register 0
SFR Address
SFR Page
Bit 1: PD, Power-Down control bit.
0: This bit could be cleared by CPU or any exited power-down event.
1: Setting this bit activates power down operation.
Bit 0: IDL, Idle mode control bit.
0: This bit could be cleared by CPU or any exited Idle mode event.
1: Setting this bit activates idle mode operation.
PCON1: Power Control Register 1
SFR Address
SFR Page
Bit 7~1: Reserved.
Bit 0: BOD, Brown-Out Detection flag.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
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SMOD1
R/W
--
7
7
R
MEGAWIN
MAKE YOU WIN
SMOD0
= All
= 0x87
= All
= 0x97
R/W
--
6
6
R
R/W
--
--
5
5
R
POF
R/W
--
4
4
R
Reset Value = 0001-0000
Reset Value = XXXX-XXX0
GF1
R/W
--
3
3
R
GF0
R/W
--
2
2
R
MG82FE(L)308/316
R/W
PD
--
1
1
R
Preliminary, v 0.04
BOD
IDL
R/W
R/W
0
0