s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 105

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

CMIE — Clock Monitor Interrupt Enable Bit
CMF — Clock Monitor Interrupt Flag
CMON — Clock Monitor On Bit
CS — Clock Select Bit
ICGON — Internal Clock Generator On Bit
ICGS — Internal Clock Generator Stable Bit
Freescale Semiconductor
This read/write bit enables clock monitor interrupts. An interrupt will occur when both CMIE and CMF
are set. CMIE can be set when the CMON bit has been set for at least one cycle. CMIE is forced clear
when CMON is clear or during reset.
This read-only bit is set when the clock monitor determines that either ICLK or ECLK becomes inactive
and the CMON bit is set. This bit is cleared by first reading the bit while it is set, followed by writing the
bit low. This bit is forced clear when CMON is clear or during reset.
This read/write bit enables the clock monitor. CMON can be set when both ICLK and ECLK have been
on and stable for at least one bus cycle. (ICGON, ECGON, ICGS, and ECGS are all set.) CMON is
forced set when CMF is set, to avoid inadvertent clearing of CMF. CMON is forced clear when either
ICGON or ECGON is clear, during stop mode with OSCENINSTOP low, or during reset.
This read/write bit determines which clock will generate the oscillator output clock (CGMXCLK). This
bit can be set when ECGON and ECGS have been set for at least one bus cycle and can be cleared
when ICGON and ICGS have been set for at least one bus cycle. This bit is forced set when the clock
monitor determines the internal clock (ICLK) is inactive or when ICGON is clear. This bit is forced clear
when the clock monitor determines that the external clock (ECLK) is inactive, when ECGON is clear,
or during reset.
This read/write bit enables the internal clock generator. ICGON can be cleared when the CS bit has
been set and the CMON bit has been clear for at least one bus cycle. ICGON is forced set when the
CMON bit is set, the CS bit is clear, or during reset.
This read-only bit indicates when the internal clock generator has determined that the internal clock
(ICLK) is within about 5 percent of the desired value. This bit is forced clear when the clock monitor
determines the ICLK is inactive, when ICGON is clear, when the ICG multiplier register (ICGMR) is
written, when the ICG TRIM register (ICGTR) is written, during stop mode with OSCENINSTOP low,
or during reset.
1 = Clock monitor interrupts enabled
0 = Clock monitor interrupts disabled
1 = Either ICLK or ECLK has become inactive.
0 = ICLK and ECLK have not become inactive since the last read of the ICGCR, or the clock monitor
1 = Clock monitor output enabled
0 = Clock monitor output disabled
1 = External clock (ECLK) sources CGMXCLK
0 = Internal clock (ICLK) sources CGMXCLK
1 = Internal clock generator enabled
0 = Internal clock generator disabled
1 = Internal clock is within 5 percent of the desired value.
0 = Internal clock may not be within 5 percent of the desired value.
is disabled.
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
Input/Output (I/O) Registers
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