s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 199

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 16
Timebase Module (TBM)
16.1 Introduction
This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user
selectable rates using a counter clocked by either the internal or external clock sources. This TBM version
uses 15 divider stages, eight of which are user selectable.
16.2 Features
Features of the TBM module include:
16.3 Functional Description
This module can generate a periodic interrupt by dividing the clock source supplied from the internal clock
generator module, TBMCLK. Note that this clock source is the external clock ECLK when the ECGON bit
in the ICG control register (ICGCR) is set. Otherwise, TBMCLK is driven at the internally generated clock
frequency (ICLK). In other words, if the external clock is enabled it will be used as the TBMCLK, even if
the MCU bus clock is based on the internal clock.
The counter is initialized to all 0s when TBON bit is cleared. The counter, shown in
counting when the TBON bit is set. When the counter overflows at the tap selected by TBR2–TBR0, the
TBIF bit gets set. If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared
by writing a 1 to the TACK bit. The first time the TBIF flag is set after enabling the timebase module, the
interrupt is generated at approximately half of the overflow period. Subsequent events occur at the exact
period.
The timebase module may remain active after execution of the STOP instruction if the internal clock
generator has been enabled to operate during stop mode through the OSCENINSTOP bit in the
configuration register. The timebase module can be used in this mode to generate a periodic wakeup from
stop mode.
16.4 Interrupts
The timebase module can periodically interrupt the CPU with a rate defined by the selected TBMCLK and
the select bits TBR2–TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE
bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt
request.
Interrupts must be acknowledged by writing a 1 to the TACK bit.
Freescale Semiconductor
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Software configurable periodic interrupts with divide-by-8, 16, 32, 64, 128, 1024, 2048, 4096, 8192,
16384, 32768, 262,144, 1,048,576, and 4,194,304 taps of the selected clock source
Configurable for operation during stop mode to allow periodic wake up from stop
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
Figure
16-1, starts
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