s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 97

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Enabling the clock monitor and clock monitor interrupts requires a flow similar to this:
These events must happen in sequence.
8.4.3 Using Clock Monitor Interrupts
The clock monitor circuit can be used to recover from perilous situations such as crystal loss. To use the
clock monitor effectively, these points should be observed:
8.4.4 Quantization Error in DCO Output
The digitally controlled oscillator (DCO) is comprised of three major sub-blocks:
Each of these blocks affects the clock period of the internal clock (ICLK). Since these blocks are controlled
by the digital loop filter (DLF) outputs DDIV and DSTG, the output of the DCO can change only in
quantized steps as the DLF increments or decrements its output. The following sections describe how
each block will affect the output frequency.
Freescale Semiconductor
1. Binary weighted divider
2. Variable-delay ring oscillator
3. Ring oscillator fine-adjust circuit
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Enable the alternate clock source
Wait for both clock sources to be stable
Switch to the desired clock source if necessary
Enable the clock monitor
Enable clock monitor interrupts
Enable the clock monitor and clock monitor interrupts.
The first statement in the clock monitor interrupt service routine (CMISR) should be a read to the
ICG control register (ICGCR) to verify that the clock monitor flag (CMF) is set. This is also the first
step in clearing the CMF bit.
The second statement in the CMISR should be a write to the ICGCR to clear the CMF bit (write the
bit low). Writing the bit high will not affect it. This statement does not need to immediately follow
the first, but must be contained in the CMISR.
The third statement in the CMISR should be to clear the CMON bit. This is required to ensure
proper reconfiguration of the reference dividers. This statement also must be contained in the
CMISR.
Although the clock monitor can be enabled only when both clocks are stable (ICGS is set or ECGS
is set), it will remain set if one of the clocks goes unstable.
The clock monitor only works if the external slow (EXTSLOW) bit in the CONFIG is set to the
correct value.
The internal and external clocks must both be enabled and running to use the clock monitor.
When the clock monitor detects inactivity, the inactive clock is automatically deselected and the
active clock selected as the source for CGMXCLK and TBMCLK. The CMISR can use the state of
the CS bit to check which clock is inactive.
When the clock monitor detects inactivity, the application may have been subjected to extreme
conditions which may have affected other circuits. The CMISR should take any appropriate
precautions.
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
Usage Notes
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