s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 155

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

LINR — LIN Receiver Bit
SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits
SCR2–SCR0 — ESCI Baud Rate Select Bits
Freescale Semiconductor
This read/write bit selects the enhanced ESCI features for slave nodes in the local interconnect
network (LIN) protocol as shown in
In LIN (version 1.2) systems, the master node transmits a break character which will appear as
11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
slave node must be within ±15% of the master node's oscillator. Since a slave node cannot know if it
is running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave
node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. The
break symbol length must be verified in software in any case, but the LINR bit serves as a filter,
preventing false detections of break characters that are really 0x00 data characters.
These read/write bits select the baud rate register prescaler divisor as shown in
clears SCP1 and SCP0.
These read/write bits select the ESCI baud rate divisor as shown in
SCR2–SCR0.
LINT
0
0
0
1
1
1
1
LINR
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
Table 13-6. ESCI LIN Slave Node Control Bits
0
1
1
0
0
1
1
SCR[2:1:0]
SCP[1:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 13-7. ESCI Baud Rate Prescaling
0 0
0 1
1 0
1 1
Table 13-8. ESCI Baud Rate Selection
M
X
0
1
0
1
0
1
Table
Normal ESCI functionality
11-bit break detect enabled for LIN receiver
12-bit break detect enabled for LIN receiver
13-bit generation enabled for LIN transmitter
14-bit generation enabled for LIN transmitter
11-bit break detect/13-bit generation enabled for LIN
12-bit break detect/14-bit generation enabled for LIN
13-6. Reset clears LINR.
Prescaler Divisor (BPD)
Baud Rate Divisor (BD)
Baud Rate Register
Functionality
128
13
16
32
64
1
3
4
1
2
4
8
Table
13-8. Reset clears
Table
13-7. Reset
I/O Registers
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