s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 197

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MODFEN — Mode Fault Enable Bit
SPR1 and SPR0 — SPI Baud Rate Select Bits
Use this formula to calculate the SPI baud rate:
where:
15.13.3 SPI Data Register
The SPI data register is the read/write buffer for the receive data register and the transmit data register.
Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register
reads data from the receive data register. The transmit data and receive data registers are separate
buffers that can contain different values. See
R7–R0/T7–T0 — Receive/Transmit Data Bits
Freescale Semiconductor
This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the
MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is set, then this pin is not available as a general purpose I/O. When the SPI is
enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of
MODFEN. (See
If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI
configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents
the MODF flag from being set. It does not affect any other part of SPI operation. (See
Fault
In master mode, these read/write bits select one of four baud rates as shown in
SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.
CGMOUT = base clock output of the internal clock generator module (ICG), see
BD = baud rate divisor
Error).
Address:
Clock Generator (ICG)
Do not use read-modify-write instructions on the SPI data register since the
buffer read is not the same as the buffer written.
Reset:
Read:
Write:
15.12.4 SS (Slave
$000F
Bit 7
R7
T7
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
SPR1:SPR0
Table 15-3. SPI Master Baud Rate Selection
Figure 15-14. SPI Data Register (SPDR)
00
01
10
11
R6
T6
6
Module.
Select)).
Baud rate
R5
T5
5
Figure 15-2
Indeterminate after Reset
NOTE
R4
T4
4
=
Baud Rate Divisor (BD)
CGMOUT
------------------------- -
2
×
BD
R3
T3
3
128
32
2
8
R2
T2
2
R1
T1
1
Table
Chapter 8 Internal
Bit 0
R0
T0
15-3. SPR1 and
15.6.2 Mode
I/O Registers
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