s908ey16g2vfar Freescale Semiconductor, Inc, s908ey16g2vfar Datasheet - Page 190

• Manufacturer Part Number: s908ey16g2vfar
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI) Module
Two sources in the SPI status and control register can generate CPU interrupt requests:
15.8 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI
configured as a master, a queued data byte is transmitted immediately after the previous transmission
has completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates when the transmit data buffer
is ready to accept new data. Write to the SPI data register only when the SPTE bit is high.
shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has
CPHA:CPOL = 1:0).
For a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having
to time the write of its data between the transmissions. Also, if no new data is written to the data buffer,
the last value contained in the shift register will be the next data word transmitted.
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1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the
register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
SPSCK (CPHA:CPOL = 1:0)
WRITE TO SPDR
READ SPSCR
READ SPDR
1
2
3
4
5
6
SPRF
CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU READS SPSCR WITH SPRF BIT SET.
SPTE
MOSI
1
Figure 15-10. SPRF/SPTE CPU Interrupt Timing
MC68HC908EY16A • MC68HC908EY8A Data Sheet, Rev. 1
MSB BIT
BYTE 1
2
6
BIT
5
3
BIT
4
BIT
3
BIT
2
BIT
1
10
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
7
8
9
LSB MSB BIT
5
4
CPU READS SPDR, CLEARING SPRF BIT.
CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
BYTE 2
6
6
7
BIT
5
8
BIT
4
BIT
3
BIT
2
BIT
1
LSB MSB BIT
10
Freescale Semiconductor
9
BYTE 3
11
6
12
Figure 15-10
BIT
5
BIT
4