pcf8833 NXP Semiconductors, pcf8833 Datasheet - Page 13

• Manufacturer Part Number: pcf8833
• Description: Stn Rgb - 132 X 132 X 3 Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
6.2
6.2.1
No operation (NOP) has no effect on internal data or settings. However, it can be used to terminate data transfer (read
and write).
Table 3 No operation command bits
6.2.2
The PCF8833 has a hardware and a software reset. After
power-up a hardware reset (pin RES) must be applied; see
Fig.50. The hardware and software resets give the same
results. After a reset, the chip has the following state:
Table 4 Reset state after hardware and software reset
2003 Feb 14
Sleep_IN
INVOFF
BSTRON
DISPON
TEOFF
IDMOFF
NORON
V
MY
RGB
MX
LAO
BRS
TRS
FINV
DOR
TCDFE
TCVOPE
EC
All LCD outputs are set to V
RAM data unchanged
Power-down mode (Sleep_IN)
Command register set to default states; see Table 4
Interface pins are set to inputs.
STN RGB - 132
COMMAND
D/C
0
Function set
N
R
O OPERATION
ESET
7
0
PCF8833 is in Sleep_IN mode (booster and display are switched off)
display inversion is off
when Sleep_OUT is active; booster is switched on
when Sleep_OUT is active; display is turned on
tearing effect line pulse is turned off
Idle mode is turned off (4 kbyte colour mode, not 8-colour mode)
Normal mode is active, not Scroll or Partial mode
RAM write in X direction
no mirror Y
colour order is RGB
no mirror X
line address order (top to bottom)
bottom rows are not mirrored; note 1
top rows are not mirrored; note 1
super frame inversion is on
normal data order
DF temperature compensation switched on
VOP temperature compensation switched on
internal oscillator
6
0
132
SS
(display off)
3 driver
5
0
DESCRIPTION
4
0
13
After a reset, care must be taken with respect to the reset
timing constraints (see Fig.50) when the PCF8833 is
powered-up. The power-up must be done by sending the
Sleep_OUT command.
After a power-up the display RAM content is undefined.
Neither a hardware reset nor a software reset changes the
data that is stored in the display RAM. Sending display
data must stop 160 ns before issuing a hardware reset,
otherwise the last word written to the display RAM may be
corrupted. The row and column outputs are tied to V
with a reset because power-down (Sleep_IN) is in the
reset state.
3
0
2
0
1
0
Objective specification
0
0
0
0
0
0
0
1
0
1
1
0
RESET STATE
0
0
PCF8833
DEFAULT
00H
SS1