pcf8833 NXP Semiconductors, pcf8833 Datasheet - Page 82

• Manufacturer Part Number: pcf8833
• Description: Stn Rgb - 132 X 132 X 3 Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
15 MODULE MAKER PROGRAMMING
The One Time Programmable (OTP) technology has been
implemented in the PCF8833. It enables the module
maker to perform an LCD supply voltage calibration after it
has been assembled on an LCD module. The module
maker can also pre-define command set registers in order
to provide the setmaker with a ‘plug and play’ module
where only display related data has to be sent.
The PCF8833 features the following module maker
programming facilities:
2003 Feb 14
handbook, full pagewidth
V
Multiplication factor S[1:0] to FS[1:0] for full Display
mode and PS[1:0]) for partial Display mode
Set VPR[8:0] to FVPR[8:0] for full Display mode and
PVPR[8:0] for partial Display mode
Set bias system VB[3:0] to FVB[3:0] for full Display
mode and PVB[3:0] for partial Display mode
Segmented temperature compensation slopes for V
SLA [2:0], SLB[2:0], SLC[2:0] and SLD[2:0]
Segmented temperature frame frequencies DFA[6:0],
DFB[6:0], DFC[6:0] and DFD[6:0]
Frame frequency 8-colour mode DF8[6:0]
STN RGB - 132
LCD
calibration
V T [ 7:0 ]
MMVOPCAL [ 5:0 ]
VCON [ 6:0 ]
V PR [ 8:0 ]
Temperature compensation V T , 8-bit value
OTP V LCD calibration, 6-bit offset
VCON register, 7-bit
V PR register, 9-bit value
132
3 driver
Fig.55 V
range 128 to 127
range 32 to 31
range 64 to 63
range 0 to 445
usable range 5 to 410
LCD
LCD
,
82
calibration.
15.1
The first feature included is the ability to adjust the V
voltage with a 6-bit code (MMVOPCAL). This code is
implemented in twos complement notation giving rise to a
positive or negative offset to the V
the circuit has underflow and overflow protection. In the
event of an overflow, the output will be clamped to
V
to 0.
Figure 55 illustrates how the high voltage generator setting
V
Section 6.2.31, Fig.55 also takes the temperature
compensation V
is reflected in the following equation:
V
VCON[6:0] + V
OP
OP
LCD
Identification bits ID2[7:0] and ID3[7:0]
TRS and BRS
Factory default bit EFD
Seal bit.
= 445; during an underflow the output will be clamped
is controlled. Compared to equation (1) in
= a + (V
V
LCD
calibration
T
[7:0] + MMVOPCAL[5:0] +
PR
T
range 0 to 445
[8:0])
into account (see Section 6.2.40), which
b
MGU971
V OP
PR
to high voltage
generator
Objective specification
register. The adder in
PCF8833
LCD