pcf8833 NXP Semiconductors, pcf8833 Datasheet - Page 72

• Manufacturer Part Number: pcf8833
• Description: Stn Rgb - 132 X 132 X 3 Driver
• Manufacturer: NXP Semiconductors

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9.2
The Read mode of the serial interface means that the microcontroller reads data from the PCF8833. The PCF8833 can send data back to the
microcontroller in two different ways. The serial bus protocol for the RDID1, RDID2, RDID3 and RDTEMP commands is illustrated in Fig.46. Descriptions
of these commands are given in Section 6.2. After a command has been issued, a byte is transmitted in the opposite direction (using SDOUT). In order
to reach the timing characteristics as given in Chapter 13 data bit b7 must be handled as a don’t care. When the speed of the clock is slowed down to
at least half of maximum speed, at least for reading b7, the reading of data bit b7 is valid.
The PCF8833 samples the SDIN data at rising SCLK edges, but shifts SDOUT data at falling SCLK edges. Thus the microcontroller is supposed to
read SDOUT data at rising SCLK edges.
After the read command has been sent, the SDIN line must be set to 3-state not later than the falling SCLK edge of the last bit (see Fig.46).
When using the RDDIDIF (see Section 6.2.6) or RDDST (see Section 6.2.7) commands the PCF8833 sends 24 or 32 data bits respectively back to the
microcontroller. The serial bus protocols for the RDDIDIF and RDDST commands are illustrated in Figs. 47 and 48. After one of these commands has
been sent 3 or 4 bytes respectively are transmitted in the opposite direction (using SDOUT) after one dummy clock cycle is given.
The 8th read bit is shorter than the others because it is terminated by the rising SCLK edge; see Figs 46, 47 and 48. The last rising SCLK edge sets
SDOUT to 3-state.
The serial interface timing diagram is illustrated in Fig.51. For the dummy read cycle the time t
SCE
SCLK
SDIN
SDOUT
Read mode
S
DC
Fig.46 Serial bus protocol, Read mode (PS[2:0] = XX0) for RDID1,RDID2, RDID3 and RDTEMP commands.
b7
b6
b5
b4
TB
b3
b2
b1
b0
b7
b6
b5
b4
TB
b3
b2
b1
b0
ACC
DC
is referenced to the rising edge of the SCLK signal.
b7
b6
b5
b4
TB
b3
b2
b1
MGU962
b0
P