ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 163

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
October 2007
Notes for
(1)
(2)
(3)
(4)
JTAG
Configuration
Table 3–4. Stratix II GX Configuration Features (Part 2 of 2)
Scheme
In these modes, the host system must send a DCLK that is 4× the data rate.
The enhanced configuration device decompression feature is available, while the Stratix II GX decompression
feature is not available.
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not
supported.
The supported download cables include the Altera USB-Blaster universal serial bus (USB) port download cable,
MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the
ByteBlasterMV parallel port download cable.
Table
3–4:
Download cable
MAX II device or microprocessor and
flash device
Configuration Method
Device Security Using Configuration Bitstream Encryption
Stratix II and Stratix II GX FPGAs are the industry’s first FPGAs with the
ability to decrypt a configuration bitstream using the AES algorithm.
When using the design security feature, a 128-bit security key is stored in
the Stratix II GX FPGA. To successfully configure a Stratix II GX FPGA
that has the design security feature enabled, the device must be
configured with a configuration file that was encrypted using the same
128-bit security key. The security key can be stored in non-volatile
memory inside the Stratix II GX device. This nonvolatile memory does
not require any external devices, such as a battery back up, for storage.
1
Device Configuration Data Decompression
Stratix II GX FPGAs support decompression of configuration data, which
saves configuration memory space and time. This feature allows you to
store compressed configuration data in configuration devices or other
(4)
An encrypted configuration file is the same size as a
non-encrypted configuration file. When using a serial
configuration scheme such as passive serial (PS) or active serial
(AS), configuration time is the same whether or not the design
security feature is enabled. If the fast passive parallel (FPP)
scheme is used with the design security or decompression
feature, a 4× DCLK is required. This results in a slower
configuration time when compared to the configuration time of
an FPGA that has neither the design security nor the
decompression feature enabled. For more information about
this feature, contact an Altera sales representative.
Design Security Decompression
Stratix II GX Device Handbook, Volume 1
Configuration & Testing
Remote System
Upgrade
3–7