ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 289

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 4–12. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
Figure 4–13. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
Altera Corporation
October 2007
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions
clock and the input clock buffer affect the output DCD.
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
(Figure
4–13). Therefore, any distortion on the input
Stratix II GX Device Handbook, Volume 1
DC and Switching Characteristics
4–119