ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 303

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
October 2007
Note to
(1)
Number of DQS Delay Buffer Stages
Table 4–114. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t
Delay stages used for request DQS phase shift are reported in a project’s Compilation Report in the Quartus II
software. For example, phase-shift error on two delay stages under -3 conditions is 50 ps peak-to-peak or 25 ps.
Table
4–114:
1
2
3
4
Notes to
(1)
(2)
Note to
(1)
Number of DQS Delay Buffer Stages
Table 4–113. DQS Jitter Specifications for DLL-Delayed Clock (t
Note (1)
Table 4–115. DQS Bus Clock Skew Adder Specifications
(t
DQS
Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on
two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps.
Delay stages used for requested DQS phase shift are reported in a project’s
Compilation Report in the Quartus II software.
This skew specification is the absolute maximum and minimum skew. For
example, skew on a 40 DQ group is 40 ps or 20 ps.
_CLOCK_SKEW_ADDER)
(1)
Table
Table
18 DQ per DQS
36 DQ per DQS
–3 Speed Grade (ps) –4 Speed Grade (ps) –5 Speed Grade (ps)
4 DQ per DQS
9 DQ per DQS
4–115:
4–113:
Mode
(2)
1
2
3
4
100
25
50
75
Stratix II GX Device Handbook, Volume 1
Commercial (ps)
120
DQS Clock Skew Adder (ps)
30
60
90
DC and Switching Characteristics
110
130
160
80
DQS
_
PSERR
)
40
70
75
95
Industrial (ps)
DQS
105
140
110
130
180
210
35
70
_
JITTER
(1)
4–133
)