ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 294

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

Duty Cycle Distortion
4–124
Stratix II GX Device Handbook, Volume 1
Note to
(1)
Note to
(1)
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
LVPECL
DDIO Column Output I/O
DDIO Column Output I/O
Table 4–102. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2)
Table 4–103. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 and
-5 Devices
Maximum DCD (ps) for
Maximum DCD (ps) for
Table 4–102
Table 4–103
Table
Table
Standard
Standard
4–102:
4–103:
assumes the input clock has zero DCD.
assumes the input clock has zero DCD.
Note (1)
Note (1)
3.3/2.5V
3.3/2.5V
140
150
150
150
125
240
180
440
390
375
325
430
355
350
335
320
330
330
330
330
180
TTL/CMOS
Input IO Standard (No PLL in the Clock Path)
TTL/CMOS
Input IO Standard (No PLL in the Clock Path)
1.8/1.5V
260
270
270
270
240
360
180
1.8/1.5V
495
450
430
385
490
410
405
390
375
385
385
390
360
180
SSTL-2
2.5V
155
180
70
60
60
55
85
SSTL-2
2.5V
170
120
105
160
180
90
85
80
65
70
60
60
60
90
SSTL/HSTL
1.8/1.5V
155
180
70
60
60
55
85
SSTL/HSTL
1.8/1.5V
HSTL12
100
180
160
110
100
155
95
75
70
65
80
70
70
70
1.2V
155
180
70
60
60
55
85
Altera Corporation
October 2007
Unit
ps
ps
ps
ps
ps
ps
ps
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps