ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 208

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

Operating Conditions
4–38
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Serial RapidIO
SDI
BASIC Single
Width
BASIC Double
Width
Table 4–21. PCS Latency (Part 2 of 2)
Functional Mode
The latency numbers are with respect to the PLD-transceiver interface clock cycles.
The total latency number is rounded off in the Sum column.
For CPRI 614 Mbps and 1.228 Gbps data rates, the Quartus II software customizes the PLD-transceiver
interface clocking to achieve zero clock cycle uncertainty in the transmitter phase compensation FIFO
latency. For more details, refer to the CPRI Mode section in the
chapter in volume 2 of the Stratix II GX Device Handbook.
Table
4–21:
10-bit channel
20-bit channel
Configuration
channel width
channel width
channel width
channel width
16-bit/20-bit
16-bit/20-bit
32-bit/40-bit
3.125 Gbps
1.25 Gbps,
8-bit/10-bit
Loopback/
2.5 Gbps,
HD, 3G
Parallel
width
width
BIST
HD
TX PIPE
Note (1)
-
-
-
-
-
-
-
-
Phase
Comp
FIFO
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
TX
Transmitter PCS Latency
Serializer
Byte
Stratix II GX Transceiver Architecture Overview
1
1
1
1
1
1
1
1
TX State
Machine
-
-
-
-
-
-
-
-
Encoder
8B/10B
0.5
0.5
0.5
0.5
1
1
1
1
Altera Corporation
Sum
October 2007
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
(2)