ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 252

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

Timing Model
4–82
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Input
delay from
pin to
internal
cells
Input
delay from
pin to
input
register
Delay
from
output
register to
output pin
Output
enable pin
delay
Parameter
Table 4–80. Stratix II GX IOE Programmable Delay on Column Pins
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the latest
version of the Quartus II software.
This column refers to –3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to –3 speed grades for EP2SGX130 devices.
Table
Pad to
I/O
dataout
to core
Pad to
I/O input
register
I/O
output
register
to pad
t
Affected
XZ
Paths
4–80:
, t
ZX
Available
Settings
64
8
2
2
IOE Programmable Delay
See
Tables 4–80
Offset
Min
Minimum
0
0
0
0
Timing
Offset
1781
2053
Max
332
320
and
Offset
Min
Grade
0
0
0
0
4–81
-3 Speed
Offset
2881
3275
for IOE programmable delay.
(2)
Max
500
483
Offset
Min
Grade
0
0
0
0
-3 Speed
Offset
3025
3439
(3)
Max
525
507
Note (1)
-4 Speed Grade
Offset
Min
0
0
0
0
Offset
3217
3657
Max
559
539
Altera Corporation
October 2007
Offset
Min
0
0
0
0
-5 Speed
Grade
3,860
Offset
4388
Max
670
647
Unit
ps
ps
ps
ps