mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 18

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

2.8.3 Other Sources of Information
Freescale publishes two application notes on related subjects:
EDN Magazine offers a reprint of the “Designer’s Guide to Electromagnetic Compatibility.”
Refer to 6 SOURCES OF INFORMATION for ordering information.
EMC consultants are probably the best source of information on this topic, since they specialize in EMC and
RFI problems. Consultants can help troubleshoot real problems, conduct seminars and provide tutorials,
books and software on the subject.
2.9 Connecting Memory and Peripherals
The MCU offers many different ways to configure memory and peripherals. The user can decode the exter-
nal bus interface externally or use chip-selects. Since it is usually more efficient to use the chip-selects, this
tutorial does not cover signal decoding. However, the SIM Reference Manual (SIMRM/AD) gives detailed
explanations and examples of how to decode signals for both 8- and 16-bit memory devices on pages 5-31
through 5-34. These examples also show how to use function code pins to determine which address space
is being accessed.
The MC68332 can generate 12 chip-select signals. These signals can be used to expand the system. A
chip-select signal selects and enables a particular peripheral device or memory chip for data transfer. The
chip-select circuits can also be programmed to generate data transfer and size acknowledge (DSACK), in-
terrupt acknowledge (IACK), and autovector (AVEC) signals.
2.9.1 Using Chip-Selects to Generate DSACK
Chip-select circuits can be configured to wait for external data and size acknowledge signals on the
DSACK1 and DSACK0 lines or to generate internal DSACK signals. A circuit can generate an internal
DSACK signal even if the pin is configured for discrete output or alternate function.
The chip-select logic can wait for a certain number of clock states before generating DSACK. These states
are called wait states. Wait states are inserted after state three of a read or write bus cycle. A normal bus
cycle lasts three clock cycles plus the number of wait clock cycles. The chip-select logic can insert a maxi-
mum of 13 wait states.
2.9.1.1 The Relationship Between Wait States And Memory Speed
Memory speed and the number of wait states necessary are related by the following equations:
In the equations, WS is the number of wait states programmed in the DSACK field. For fast termination
mode, WS = –1, for zero wait states, WS = 0, for one wait state, WS = 1, etc. Also, it is assumed that chip-
select assertion is based on address strobe. If it is based on data strobe, add 2(t
cycle chip-select access time. The other known parameters are shown in Table 2.
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• Localize any high frequency circuits, such as the clock and address or data buses. Decouple locally
• Turn off any output signals (such as ECLK) that are not used.
• Shield the board externally.
• Reduce power supply noise as much as possible.
Designing for Electromagnetic Compatibility with HCMOS Microcontrollers (AN1050/D)
Transmission Line Effects in PCB Applications (AN1051/D).
Address access time = (2.5 + WS) X t
Chip-select access time (MCU read cycle) = (2 + WS) X t
Chip-select access time (MCU write cycle) = (2 + WS) X t
using high frequency filters such as ferrite chokes or damping resistors. Be sure to separate the high
speed and low speed circuits.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
CYC(min)
– t
CHAV(max)
CYC(min)
CYC(min)
– t
DICL(min)
– t
– t
CLSA(max)
CLSA(max)
CYC
– t
+ t
) to t
DICL(min)
CLSN(min)
M68331/332TUT/D
CLSA
MC68331/332
for the write