mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 22

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

2.10 Using External Interrupts
The MCU has seven external interrupt lines, IRQ[7:1]. These are active low signals that cause the processor
to jump to a special routine and then return to the main code. The following paragraphs cover the basic el-
ements of servicing external interrupt service requests. Refer to 4.1.1 Exceptions for more detail. Chapter
6 of the SIM Reference Manual (SIMRM/AD) has an in-depth explanation of how to use external interrupts.
2.10.1 Interrupt Priority Levels
An interrupt can be recognized on one of seven priority levels. These levels correspond to the numeric val-
ues of the external interrupt request lines. Level one (IRQ1) has the lowest priority; level seven (IRQ7) has
the highest priority level. Levels one through six can be masked by the interrupt priority level (IPL) field con-
tained in bits ten through eight of the CPU status register (SR). The level specified in the IPL field and all
levels below it are masked and are not recognized by the CPU. Level seven is the only exception to this
rule; it cannot be masked. Out of reset, the IPL field is set to level seven. Thus, levels one through six will
not be recognized unless the IPL field is re-written to a lower value. The priority mask value can be changed
by writing a new value into the appropriate bits of the SR.
To allow interrupts on levels six and seven only, mask out levels five and below.
2.10.2 Interrupt Arbitration Field
Most modules in the MCU can request interrupt service. The CPU treats external interrupts as interrupt ser-
vice requests from the system integration module. The interrupt arbitration (IARB) field in the configuration
register of each module determines which module's interrupt requests take precedence when the CPU re-
ceives more than one request at the same priority level. In order for interrupt requests to be acknowledged,
each module must be assigned a unique IARB number between $1 (lowest precedence) and $F (highest
precedence). Out of reset, the SIM IARB field has an initial value of $F, while other modules have initial
IARB values of $0.
22
Figure 15 Configuring 16-Bit Memory with 8-Bit RAMs — Separate Read and Write Enables
ADDR[16:0]
MCU
DATA[15:0]
CSBOOT
CS0
CS1
CS2
ANDI.W #$F8FF, SR
ORI.W #$0500, SR
UPPER BYTE ENABLE
LOWER BYTE ENABLE
READ ENABLE (BOTH BYTES)
ROM ENABLE
Freescale Semiconductor, Inc.
DATA[15:8]
For More Information On This Product,
ADDR[13:1]
DATA
WE
Go to: www.freescale.com
32K X 8
RAM
OE
ADDR
CE
EXAMPLE:
DATA[7:0]
ADDR[13:1]
DATA
WE
32K X 8
RAM
OE
ADDR
CE
DATA[15:0]
DATA
32K X 16
M68331/332TUT/D
ROM
ADDR
CE
MC68331/332
332TUT EXT MEM CONN 3
ADDR[16:1]