mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 3

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

2.1 Using Data Bus Pins to Configure the MCU
The logic level of the data bus pins during reset determines many important operating characteristics of the
MCU. Ensuring that the data bus is in a known condition during reset is vital to proper operation because
the state of each data bus pin is sampled on the rising edge of the RESET signal. The data bus pins have
weak internal pull-up circuitry that should cause them to default to a logic one if left floating (the pull-up cur-
rent is 15 to 120 A). However, since it is possible for external bus loading to overcome these internal pull-
ups, it is a good idea to drive data bus pins that are critical to successful operation of the application to a
known condition during reset and for at least five ns afterwards (there is a five ns hold time requirement after
the release of RESET for a data bus pin to be recognized at a particular logic level). Table 1 shows how
each data bus pin affects the system configuration.
As an example, Table 1 shows that the state of data bus pin 0 (DATA0) during reset determines whether
CSBOOT operates as a 16-bit chip-select or as an 8-bit chip-select. Likewise, data bus pin 1 (DATA1) de-
termines whether the CS0/BR, CS1/BG, and CS2/BGACK pins function as chip-select lines or as bus con-
trol signals. After reset, software can make other selections for these pins by writing to a pin assignment
register.
A simple method of pulling a data bus pin high is to connect a 10 K
supply. Although putting a resistor on a data bus pin degrades performance at higher frequencies, many
designers use resistive pull-ups without significant side effects. The preferred method of driving data bus
pins during reset is by means of an active driver. A circuit to perform this function is shown in Figure 1 . This
circuit uses a 3-state buffer, such as a 74HC244 non-inverting octal driver, and meets the five ns hold time
requirement. While this method does require external circuitry, it is recommended when high levels of noise
may be encountered or when high reliability of operation is an overriding concern.
MC68331/332
M68331/332TUT/D
Notes:
Mode Select Pin
1. Only one data bus pin in this group needs to be driven low to select the alternate function for any of the affected
2. Slave mode is not a supported mode; it is used for factory testing. The slave mode must not be used in a cus-
MODCLK
pins. For example, to select ADDR[21:19] instead of CS[7:6], drive DATA5 low at the release of reset, and pull
DATA3, DATA4, DATA6, and DATA7 high.
tomer application.
DATA11
DATA3
DATA0
DATA1
DATA2
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
BKPT
1
DSACK0, DSACK1, AVEC, DS, AS, SIZE
Default Function (Pin Left High)
Freescale Semiconductor, Inc.
2 DESIGNING THE HARDWARE
Background Mode Disabled
For More Information On This Product,
CSBOOT is 16-bit port
Slave Mode Disabled
VCO = System Clock
IRQ[7:1], MODCLK
Table 1 Reset Mode Selection
CS[10:6]
CS[7:6]
CS[8:6]
CS[9:6]
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CS0
CS1
CS2
CS3
CS4
CS5
CS6
2
Alternate Function (Pin Pulled Low)
resistor between it and the five volt
Background Mode Enabled
EXTAL = System Clock
Slave Mode Enabled
CSBOOT is 8-bit port
PORTE I/O pins
PORTF I/O pins
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
ADDR19
BGACK
FC0
FC1
FC2
BG
BR
2
3