mc68336 Freescale Semiconductor, Inc, mc68336 Datasheet - Page 44

• Manufacturer Part Number: mc68336
• Description: An Introduction To The Mc68331 And Mc68332
• Manufacturer: Freescale Semiconductor, Inc

4.6.1 Control Registers
The TPU has several control registers that are shared by all 16 channels. Some of these registers, such as
the channel interrupt enable register and channel interrupt status register, are not always used. However,
the TPU module configuration register, the channel function select registers, the host sequence registers,
the host service request registers, and the channel priority registers should always be initialized. With the
exception of the channel interrupt status register, all writes to the TPU registers must be word-length oper-
ations. If a byte write is attempted, the value $FF will be written to the other half of the register.
4.6.1.1 The TPU Module Configuration Register
The TPU module configuration register (TPUMCR) determines important operating characteristics, such as
prescaler values for timer count registers TCR1 and TCR2, and the interrupt arbitration number. It also de-
termines whether TPU registers reside in supervisor space or in user space. The TPUMCR itself resides in
supervisor space. See 4.1 Configuring the Central Processing Unit for more information concerning
user and supervisor space.
4.6.1.2 Channel Function Select Registers
Channel function select registers (CFSR[1:3]) contain the function numbers assigned to each individual
channel. These function numbers are mask-set dependent because they are determined by the microcode
assembly.
4.6.1.3 Host Sequence Registers
Host sequence registers (HSQR0 and HSQR1) contain the host sequence bits for the function running on
a particular channel. The host sequence bits determine the mode of a particular function. Host sequence
bit encoding for each function is determined by microcode, and differs from function to function. For exam-
ple, host sequence bits for a function that counts input transitions could determine whether the function op-
erates in single-shot mode or continuous mode.
4.6.1.4 Host Service Request Registers
Host service request registers (HSRR0 and HSRR1) contain the service request bits for each channel. The
service request bits ask the TPU microengine to perform a particular service on the associated channel.
Usually, the first service request is for initialization. Another common service request is for an immediate
update.
Like host sequence bits, host service bit encoding for each function is determined by microcode, and differs
from function to function. However, the host service bits are different from other control bits because, while
the CPU can set the service bits, only the TPU can clear them. In fact, the TPU tells the CPU that it has
serviced a channel the first time by clearing the host service request bits. An HSRR should not be written
unless all of the other parameters and control bits are initialized or the associated channel is disabled (via
the channel priority register) and the host service bits are cleared. The CPU program must wait until a pre-
vious service request has been cleared before issuing a new service request.
To make a host service request, follow one of the following scenarios.
To initialize two or more channels that share a host service request register, either write all the fields in the
register at the same time or disable all channels via the channel priority registers, write to the host service
request register, then enable each channel as needed via the channel priority registers. This ensures that
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1. To initialize a channel out of reset, first initialize the parameter RAM and other control registers, then
2. To change the function operating on a particular channel, first disable the channel using the channel
3. To make a host service request other than that for initialization, do not disable the channel. Instead,
make the host service request for initialization. The final step is to enable the channel via the channel
priority register.
priority register, then follow the same steps as for initialization out of reset.
wait for the TPU to clear the previous host service request. Then, issue a new request. Usually this
is for an immediate update or to force an output state on a particular pin.
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M68331/332TUT/D
MC68331/332