at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 101

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

USB Device Operating modes
Introduction
Power-On and Reset
Speed Identification
7632C–MP3–11/06
The USB device controller supports high speed and full speed data transfers. In addition
to the default control endpoint, it provides six other endpoints, which can be configured
in control, bulk, interrupt or isochronous modes:
•
•
•
The controller starts in the “idle” mode. In this mode, the pad consumption is reduced to
the minimum.
Figure 59 shows the USB device controller main states after power-on.
Figure 59. USB Device Controller Reset State Machine
The reset state of the Device controller is:
•
•
•
•
The D+ or D- pull-up will be activated as soon as the DETACH bit is cleared and VBUS
is present.
The macro is in the ‘Idle’ state after reset with a minimum power consumption and does
not need to have the PLL activated to enter in this state.
The USB device controller can at any time be reset by clearing USBE.
The high-speed reset is managed by the hardware. At the connection, the host makes a
reset that can be:
•
•
Endpoint 0:
programmable size FIFO up to 64 bytes, default control endpoint.
Endpoints 1 and 2:
programmable size FIFO up to 512 bytes in ping-pong mode.
Endpoints 3 to 6:
programmable size FIFO up to 64 bytes in ping-pong mode.
the macro clock is stopped in order to minimize the power consumption (FRZCLK
set)
the USB device controller internal state is reset (all the registers are reset to their
default value. Note that DETACH is set.)
the endpoint banks are reset
the D+ or D- pull up are not activated (mode Detach)
a classic reset (Full-speed) or
a High-speed reset (High-speed).
RESET
HW
USBE=0
Reset
USBE=0
state>
other
<any
USBE=1
UID=1
Idle
AT85C51SND3B
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