at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 179

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Spare Zone Mode 1
Spare Zone Mode 2
Spare Zone Mode 3
7632C–MP3–11/06
The spare zone is not managed by the NFC. The data zone is contiguous.
The user sends the commands to prepare the page for read or write. The data flow
starts when the READ or WRITE bits are set by the user (write in NFACT). The NFC did
not manage the spare zone, and did not stop when the ECC FIFO is full. Thus, NFC
stops when it reaches the end of the data zone, or when it receives a STOP action.
The spare zone is entirely managed by the NFC. The ECC is computed when the data
flow starts. Each 256 bytes met, a 3-bytes ECC is built and stored in an ECC FIFO.
When the ECC FIFO is full, the NFC stops the flow control to the DFC, and process the
spare zone (ECC, logical value, parity... described later).
If the data flow stops before the end of the data zone, the user has the responsibility to
stop the NFC and to program the spare zone.
The NFC will stop (idle mode) when it meet the end of the page. In this case, according
to NECC, the controller will program/verify the appropriate spare zone(s). Let’s take an
example with 2kB memories:
•
•
•
Note that;
•
•
This mechanism ensures that the ECC is verified when it is valid.
This mode is particularly well suited for 512B and 2kB memories. For other kind of mem-
ories, mode 3 is preferable.
The spare zone is not automatically managed by the NFC. The ECC is computed and
stored in the ECC FIFO. When the ECC FIFO is full, the flow control is stopped and an
interrupt is sent. The NFC returns to the idle state.
For 512B memories, the ECCRDYI interrupt is always triggered after 512 data bytes
seen.
For 2kB memories and higher memories, the ECCRDYI interrupt is always triggered
after 2048 data bytes seen.
The ECC engine is reset after a write in the NFCMD register. NECC gives the number of
ECC in the FIFO.
Depending on the mapping of the page, the user have the possibility to:
•
SPZEN
if the flow starts from the beginning of the page, NECC is 4 and the 4 spare zones
will be verified or checked
if the flow starts at offset 512, NECC is 3 and the 3 last spare zones of the page be
verified or checked.
etc.
For WRITE session, the byte at offset 2 is written to 0 (ECC valid) when the spare
zone is written.
For READ session, the ECC is verified only if the ECC is valid (byte at offset 2 is 0).
send the right events to program/verify the spare zone (reading the ECC FIFO). The
READ or WRITE bits must be set (write in NFACT) to resume the data transfer, until
the end of the page or an STOP action. The firmware shall also re-initialize the ECC
FIFO by writing to NFECC.
0
1
ECCEN
1
0
ECCRDYE Description
X
0
Not Supported
This configuration is reserved and must not be programmed.
Not Supported
This configuration is reserved and must not be programmed.
AT85C51SND3B
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