at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 195

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Data Line Controller
Bus Width Control
FIFO Implementation
7632C–MP3–11/06
MMCON0.6
TX/RX Ptr
DPTRR
As shown in Figure 89, the data line controller is based on a 16-Byte FIFO used both by
the data transmitter channel and by the data receiver channel.
Data transfer can be handled in transmission or received by the Data Flow Controller
(see Section “Data Flow Controller”, page 78) or by the C51 using MMDAT register.
Figure 89. Data Line Controller Block Diagram
The data line controller supports the SD card and the new MMC 4.0 4-bit bus mode
allowing higher transfer rate. The 4-bit bus width is controlled by software by setting the
DBSIZE1:0 bits in MMCON2 register according to Table 220. In case of 1-bit bus width
(card default), SDDAT0 is used as SDDAT line and SDDAT3:1 lines are released as I/O
port.
Table 220. Data Bus Size
The 16-Byte FIFO is managed using 1 pointer and four flags indicating the status ready
of whole or half FIFO.
Pointer value is not accessible by software but can be reset at any time by setting and
clearing DPTRR bit in MMCON0 register. Resetting the pointer is equivalent to abort the
writing or reading of data.
FIFO flags indicate when FIFO is ready to be read in receive mode or to be written in
transmit mode. WFRI is set when 16 bytes are available in writing or reading. HFRI is
set when 8 bytes are available. These flags are cleared when read. These flags may
generate an interrupt request as detailed in Section “Interrupt”. WFRS and HFRS give
the status of the FIFO. They are set when respectively 16 bytes or 8 bytes are ready to
be read or written depending on the receive or transmit mode.
MMINT.3
MMINT.2
WFRI
HFRI
16-Byte
MMDAT
FIFO
MMSTA.1
MMSTA.0
WFRS
HFRS
DBSIZE1:0
2-3
0
1
MMCON0.2
CRC16 and Format
MMSTA.3
DFMT
DATFS
Data Converter
CBUSY
MMSTA.5
// -> 1-bit/4-bit
Checker
MBLOCK
MMCON0.3
CRC16S
MMSTA.4
Finished State Machine
Bus Size
1-bit SDDAT0 data bus.
4-bit SDDAT3:0 data bus.
Reserved for future use, do not program these values.
DATA Line
MMCON1.2
DATEN
Data Converter
1-bit/4-bit -> //
MMCON2.4:3
Generator
DBSIZE1:0
CRC16
MMCON1.3
DATDIR
AT85C51SND3B
MMCON1.7:4
BLEN11:0
MMBLP7:0
MMINT.4
MMINT.1
EOFI
EOBI
SDDAT3:0
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