at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 210

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

“SA0= H” Mode
“SA0= L” Mode
CPU Transfer
DFC Transfer
210
AT85C51SND3B
Figure 102. Write Data Sampling Configuration
The “SA0= H” mode is particularly fitting control management over a protocol.
Figure 103 shows a data cycle from host to device. Prior to send any data bytes, the
host must take care of the PSI state by reading the AT85C51SND3B with SA0 signal
set. This returns PSISTH: the host status register content. While PSHBSY bit in PSISTH
is set, the host must not start sending data.
As soon as PSHBSY bit is released, the host can send up to 16 bytes of data.
First data writing automatically sets PSBSY flag in PSISTA and consequently PSHBSY
bit so that host knows that system is now busy and processing. An interrupt can be gen-
erated when PSBSY flag is set by enabling PSBSYE bit in PSICON while global PSI
interrupt is enabled in IEN1 (see Figure 104).
The software can start reading and process the data after first byte reception. As soon
as data processing is done, PSBSY flag is cleared and consequently PSHBSY bit so
that host knows that system has finished processing. A software status can have been
previously written to PSISTH for reporting to the host.
Note:
Figure 103. Data Management (SA0 = H)
The “SA0= L” mode is particularly fitting data transfer with huge amount of data. Trans-
fer can be done in read and write using the DFC for high throughput or the CPU. After
control processing (PSBSY cleared) and relying to the protocol, the host starts transfer-
ring data. In all cases the host which is the master controls the data transfer by reading
from or writing to the slave.
In case of transfer handled by the CPU, the data transfer is done byte by byte. As the
host runs usually quicker than the slave, a software handshake must be established to
avoid underrun or overrun condition.
In case of transfer handled by the DFC, the slave can acknowledge its control process-
ing (PSBSY cleared) as soon as destination (host write) or source (host read) is ready.
CPU Read
PSEMPTY
Host Write
SA0 = H
PSBSY
If software reading is quicker than host writing, PSEMPTY bit must be polled before read-
ing new data byte.
PER CLK
SD7:0
SWR
SCS
Data Sampling
Up to 16 bytes
PSWS2:0
0
1
2
3
Write Data
4
Software Treatment
5
6
7
Clear PSBSY
7632C–MP3–11/06