at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 106

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

STALL Handshake and Retry
Mechanism
CONTROL Endpoint
Management
Control Write
106
AT85C51SND3B
USB line
RXSTPI
RXOUTI
TXINI
SETUP
SETUP
HW
This function is compliant with the Chapter 8 test from PMTC that send extra status for a
GET_DESCRIPTOR. The firmware sets the STALL request just after receiving the sta-
tus. All extra status will be automatically STALL’ed until the next SETUP request.
The Retry mechanism has priority over the STALL handshake. A STALL handshake is
sent if the STALLRQ request bit is set and if there is no retry required.
A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI
interrupt is triggered (if enabled). The RXOUTI interrupt is not triggered.
The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints. The firmware
shall thus never use them on that endpoints. When read, their value is always 0.
CONTROL endpoints are managed by the following bits:
•
•
•
CONTROL endpoints should not be managed by interrupts, but only by polling the sta-
tus bits.
The next figure shows a control write transaction. During the status stage, the controller
will not necessary send a NAK at the first IN token:
•
•
RXSTPI is set when a new SETUP is received. It shall be cleared by firmware to
acknowledge the packet and to clear the endpoint bank.
RXOUTI is set when a new OUT data is received. It shall be cleared by firmware to
acknowledge the packet and to clear the endpoint bank.
TXINI is set when the bank is ready to accept a new IN packet. It shall be cleared by
firmware to send the packet and to clear the endpoint bank.
If the firmware knows the exact number of descriptor bytes that must be read, it can
then anticipate on the status stage and send a ZLP for the next IN token,
or it can read the bytes and poll NAKINI, which tells that all the bytes have been
sent by the host, and the transaction is now in the status stage.
SW
OUT
HW
SW
DATA
OUT
HW
SW
NAK
IN
STATUS
SW
IN
7632C–MP3–11/06