at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 24

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Reset
Reset Source Reporting
Pads Level Control
External RST Input
24
AT85C51SND3B
In order to secure the product functionality while in power-up or power-down phase or
while in running phase, a number of internal mechanisms have been implemented.
These mechanisms are listed below and detailed in the following paragraphs.
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Figure 12 details the internal reset circuitry.
In order for the firmware to take specific actions depending on the source which has cur-
rently reset the device, activated reset source is reported to the CPU by EXTRST,
WDTRST, and PFDRST flags in PSTA register.
Figure 12. Internal Reset Circuitry
As soon as one reset source is asserted, the pads go to their reset value. This ensures
that pads level is steady during reset (e.g. NFWP set to low level and then protecting
Nand Flash against spurious writing).
The status of the Port pins during reset is detailed in Table 19.
Table 19. Pin State Under Reset Condition.
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a
low level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter… and to unpredictable behavior of
the microcontroller. A proper device reset initializes the AT85C51SND3B and vectors
the CPU to address 0000h. RST input has a pull-up resistor allowing power-on reset by
simply connecting an external capacitor to V
be applied either directly on the RST pin or indirectly by an internal reset source such as
the watchdog timer. Resistor value and input characteristics are discussed in the
Section “DC Characteristics”, page 242.
DCPWR
Port 0
Float
HVDD
LVDD
VBAT
External RST input
Power Fail Detector (brown-out)
Watchdog timer
Pads control
RST
Port 1
H
IOVDD
ON/OFF
DC-DC
1.8V
Reg
R
RST
Port 2
H
WDT
PFD
Port 3
H
OUT
TO
Port 4
H
SS
as shown in Figure 13. A warm reset can
Port 5
WDTRST
EXTRST
PFDRST
H
PSTA.1
PSTA.2
PSTA.0
NFD7:0
Float
SYSRST
NFWP
To CPU Core
To Peripherals
To Pads Control
L
7632C–MP3–11/06
NFCE0
H