at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 197

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Data Transmission
End of Transmission
Busy Status
7632C–MP3–11/06
Transmission is enabled by setting DATEN bit in MMCON1 register. FIFO must be filled
after this flag is set.
If at least the FIFO is half full, data is transmitted immediately when the response to the
write command has already been received, or is delayed after the reception of the
response if its status is correct. In both cases transmission is delayed if a card sends a
busy state on the data line until the end of this busy condition.
According to the MMC specification, the data transfer from the host to the card may not
start sooner than 2 MMC clock periods after the card response was received (formally
N
DATD1:0 bits in MMCON2 register from 3 MMC clock periods when DATD1:0 bits are
cleared to 9 MMC clock periods when DATD1:0 bits are set, by step of 2 MMC clock
periods.
In data stream mode, the end of a data frame transmission is signalled by the EOFI flag
in MMINT register. This flag may generate an interrupt request as detailed in
Section “Interrupt”. It is set, after reception of the End bit. This assumes that the STOP
command has previously been sent to the card, which is the only way to stop stream
transfer.
In data single block mode, the end of a data frame transmission is signalled by the EOFI
flag in MMINT register. This flag may generate an interrupt request as detailed in
Section “Interrupt”. It is set after the end of busy signal on SDDAT0 line.
After reception of the CRC status token, two other flags in MMSTA register: DATFS and
CRC16S report a status on the frame sent. DATFS indicates if the CRC status token for-
mat is correct or not, and CRC16S indicates if the card has found the CRC16 of the
block correct or not. CRC16S must by reset by software by setting DCR bit in MMCON2
register.
EOBI flag in MMINT register is also set at the same time as EOFI, and may generate an
interrupt request as detailed in Section “Interrupt”
In data multi block mode, the end of a data frame transmission is signalled by the EOFI
flag in MMINT register. This flag may generate an interrupt request as detailed in
Section “Interrupt”. It is set after the end of busy signal on SDDAT0 line.This assumes
that the STOP command has previously been sent to the card, which is the only way to
stop stream transfer.
The end of a block transmission is signalled by the EOBI flag in MMINT register. This
flag may generate an interrupt request as detailed in Section “Interrupt”. It is set after the
end of busy signal on SDDAT0 line.
After reception of the CRC status token of a block, two other flags in MMSTA register:
DATFS and CRC16S report a status on the frame sent. DATFS indicates if the CRC sta-
tus token format is correct or not, and CRC16S indicates if the card has found the
CRC16 of the block correct or not. CRC16S must by reset by software by setting DCR
bit in MMCON2 register.
The card uses a busy token during a block write operation. This busy status is reported
by the CBUSY flag in MMSTA register.
The busy signal is set to 0 by the card after the CRC token. At the end of busy signal,
the flag DATEN is cleared and EOFI flag is set.
Note:
WR
parameter). To address all card types, this delay can be programmed using
some cards do not respect MMC specification, and the busy status is reported too late on
the dat0 line, considering the N
tus of the card must be asked with a card command.
st
parameter. So CBUSY flag is not set. In this case, sta-
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