at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 30

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

PLL Programming
System Clock Generator
30
AT85C51SND3B
Figure 18. PLL Block Diagram and Symbol
Table 24. PLL Reverse Clock Selection
The PLL is programmed depending on the oscillator clock frequency. In order to mini-
mize the output jitter, F
programming values and reverse frequency depending on some oscillator frequency.
Table 25. PLL Programming Values versus Input Frequency
In order to increase the system computation throughput, it is possible to switch the sys-
tem clock to higher value when PLL is enabled. System clock generator block diagram
is shown in Figure 19 and is based on a frequency selector controlled by SYSCKS1:0
bits in CKSEL (see Table 34) according to Table 26.
The CPU clock can be disabled by entering the idle reduction mode as detailed in the
Section “Power Management”, page 19.
Note:
F
OSC
PLLCKS1:0
In order to prevent any incorrect operation while dynamically switching the system fre-
quency, user must be aware that all peripherals using the peripheral clock as time
reference (timers, etc…) will have their time reference modified by this frequency
change.
PLLCLK.3:0
N Divider
PLLN3:0
19.2
19.5
12
13
16
20
24
26
(MHz)
00
01
10
11
F
REV
REV
PLLCKS1:0
CKSEL.4:3
PLLCKS1:0
PFLD
Clock Selection (F
12 MHz (default)
16 MHz
20 MHz
12 MHz
must be as higher as possible. Table 26 shows the PLL
00
01
10
11
00
01
10
00
11
11
11
11
÷
Down
(PLLR + 1)
Up
R Divider
PLLCLK.7:4
PLLR3:0
12 MHz
16 MHz
20 MHz
PLLN3:0 / N
REV
1100 / 13
1100 / 13
1100 / 13
CHP
0001 / 2
0111 / 8
)
0000
0000
0000
Primary
Divider
PLLR3:0 / R
1011 / 12
0100 / 5
0101 / 6
0111 / 8
VCO
XXXX
XXXX
XXXX
XXXX
PLL Clock Symbol
CLOCK
PLL
7632C–MP3–11/06
F
REV
480 MHz
2.4
1.5
12
16
20
12
1
2
(MHz)