at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 110

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

“Autoswitch” Mode
Detailed Description
Standard Mode without
AUTOSW
110
AT85C51SND3B
Example with 1 IN data bank
Example with 2 IN data banks
FIFOCON
FIFOCON
TXINI
TXINI
SW
SW
write data from CPU
write data from CPU
NAK
BANK 0
BANK 0
writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the
data. If the IN Endpoint is composed of multiple banks, this also switches to the next
data bank. The TXINI and FIFOCON bits are automatically updated by hardware
regarding the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware
can write data to the bank, and cleared by hardware when the bank is full.
In this mode, the clear of the FIFOCON bit is performed automatically by hardware each
time the Endpoint bank is full. The firmware has to check if the next bank is empty or not
before writing the next data. On TXINI interrupt, the firmware fills a complete bank. A
new interrupt will be generated each time the current bank becomes free.
In this mode (AUTOSW cleared), the data are written by the CPU, following the next
flow:
•
•
•
When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled
(TXINE set) and TXINI is set. The CPU can also poll TXINI or FIFOCON, depending
the software architecture choice,
The CPU acknowledges the interrupt by clearing TXINI,
The CPU can write the data into the current bank (write in UEDATX),
SW
SW
IN
IN
SW
write data from CPU
BANK 1
(bank 0)
(bank 0)
DATA
DATA
SW
HW
HW
ACK
ACK
SW
SW
write data from CPU
write data from CPU
IN
BANK 0
BANK0
(bank 1)
DATA
SW
IN
7632C–MP3–11/06
ACK