tza3015hw NXP Semiconductors, tza3015hw Datasheet - Page 15

• Manufacturer Part Number: tza3015hw
• Description: 30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Reference clock programming
The reference clock, connected to pins CREF(Q), is used
for both the DCR frequency window detector and the
transmitter synthesizer. The reference clock is divided by
divider R. Pre-programmed operating in an SDH/SONET
application assumes the use of a reference clock with a
frequency that is a multiple (R) of 19.44 MHz. For other
applications, any reference frequency between
18 and 21 MHz may be used. If a reference frequency is
selected, any bit rate between 30 Mbit/s and 3.2 Gbit/s is
supported.
The division ratio and reference frequency can be
programmed by the bits FREFI2C[2:0] of register REFDIV
(A1h) or by pins FREF0 and FREF1. Internally, the
reference frequency is always divided to the lowest
frequency range between 18 and 21 MHz and for
SDH/SONET applications to 19.44 MHz. This is done by
divider R which is set by the described pins and bits.
In the pre-programmed mode (Table 6) four ranges of
clock frequencies can be used by programming R through
pins FREF0 and FREF1. In I
additional ranges of clock frequencies can be used by
programming R through bits FREFI2C[2:0].
Table 6 Truth table for reference divider R in
Table 7 Truth table for reference divider R in I
2003 Dec 16
FREF1 FREF0
0
0
0
0
1
1
FREF
HIGH
HIGH
LOW
LOW
I2C2
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
PIN
pre-programmed mode
mode
0
0
1
1
0
0
FREF
HIGH
HIGH
LOW
LOW
I2C1
BIT
0
1
0
1
0
1
DIVISION
FREF
FACTOR
I2C0
32
R
1
2
8
1
2
4
8
16
32
2
DIVISION
FACTOR
C-bus mode (Table 7) two
SDH/SONET
R
155.52
622.08
(MHz)
19.44
38.88
FREQUENCY
REFERENCE
18 to 21
36 to 42
72 to 84
144 to 168
288 to 336
576 to 672
RANGE (MHz)
FREQUENCY
REFERENCE
144 to 168
576 to 672
2
RANGE
18 to 21
36 to 42
C-bus
(MHz)
15
Reference input
For optimum jitter performance and Power Supply
Rejection Ratio (PSRR), the sensitive reference input
should be driven differentially (see Fig.9). If the reference
frequency source (f
or CREFQ input should be terminated with an impedance
which matches the source impedance R
can be improved by AC coupling the reference frequency
source to inputs CREF and CREFQ. Any low frequency
noise injected from the f
by the resulting high-pass filter. The low cut-off frequency
of the AC coupling must be lower than the reference
frequency, otherwise the reference signal will be
attenuated and the signal to noise ratio will be reduced.
The value of coupling capacitor C is calculated using the
formula:
Prescaler outputs
The prescaler output RXPRSCL(Q) is the VCO frequency
of the DCR divided by the main division factor N. It can be
used as an accurate reference for another PLL, since it
corresponds to the recovered data rate. If needed, the
polarity of the prescaler outputs can be inverted by bit
RXPRSCLINV of register DDR&RXPRSCL (D5h).
If no prescaler information is desired, the output can be
disabled by bit RXPRSCLEN of the same register. Apart
handbook, halfpage
Fig.9
50
C
Reference input with single-ended clock
source.
---------------------------------- -
2 R
on-chip
50
source
43
42
1
ref
) is single-ended, the unused CREF
V CCD
CREF
CREFQ
off-chip
ref
f
ref
power supply will be attenuated
C
C
Preliminary specification
TZA3015HW
R source
source
. The PSRR
V CC
R source
f ref
MDB060