tza3015hw NXP Semiconductors, tza3015hw Datasheet - Page 26

• Manufacturer Part Number: tza3015hw
• Description: 30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
I/O configuration
LVDS
Several options exist that allow flexible configuration of the
LVDS outputs: output amplitude, signal polarity, bus order,
mute and selective enable/disable of various outputs. All
these options can be set in the registers MFOBCON (A4h),
DMXCON (B8h), RXMFOUTC0 (D4h), DDR&RXPRSCL
(D5h) and TXMFOUTC (F2h). Affected by these registers
are:
2003 Dec 16
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handbook, full pagewidth
Parallel clock output; pins RXPC(Q)
Parallel data output; pins RXPD0(Q) to RXPD3(Q)
Frame pulse output; pins RXFP(Q)
Parity output; pins RXPAR(Q)
Parity error output; pins TXPARERR(Q)
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
OUTPUTS
DCR
from
CLUPPLLINV
serial
serial
serial
clock
data
data
I
2
C bit:
FREQUENCY
DETECTOR
LIMITER
PHASE
Fig.20 Clean-up PLL application with the TZA3015HW.
DCR
CLUPPLLHG
Fig.21 Clean-up loop back mode.
CHARGE
I
PUMP
2
C bit:
clock
clock
data
data
IPUMP
MULTIPLEXER
26
C1
R
The output swing of all LVDS outputs can be set by pin
LOWSWING or by programming bit LOWSWING in
register MFOBCON (A4h). I
programming bit I2CLOWSWING in register MFOBCON
(A4h). The typical voltage levels are given in Table 19. See
also Figs 34 and 35.
Table 19 Truth table for pin LOWSWING
DEMULTIPLEXER
external components
LOWSWING
SYNTHESIZER
Transmitter parallel clock output; pins TXPCO(Q)
Prescaler DCR output; pins RXPRSCL(Q)
Prescaler synthesizer output; pins TXPRSCL(Q).
HIGH
LOW
C2
4
VDSGLA type
e.g. Vectron
VCXO
LVDS OUTPUT VOLTAGE SWING
CREF
4
4
REFERENCE
2
DIVIDER
C-bus control is enabled by
4
4
Preliminary specification
500 mV
300 mV
TZA3015HW
parallel
data
parallel
clock
parallel
data
parallel
clock
MCE420
MCE419
to
synthesizer