tza3015hw NXP Semiconductors, tza3015hw Datasheet - Page 30

• Manufacturer Part Number: tza3015hw
• Description: 30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
A
Figure 23 shows the definition of an acknowledgement on
the I
start and stop conditions during a write from the transmitter
to the receiver. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
2003 Dec 16
handbook, full pagewidth
handbook, full pagewidth
CKNOWLEDGE
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
2
C-bus. Only one data byte is transferred between the
BY TRANSMITTER
SDA
SCL
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
START condition
S
Fig.23 (Not) acknowledge condition on the I
condition
START
S
Fig.22 Start and stop conditions.
1
30
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked
out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
2
not acknowledge
STOP condition
2
acknowledge
C-bus.
8
P
acknowledgement
clock pulse for
MBC622
9
Preliminary specification
MBC602
SDA
SCL
TZA3015HW