tza3015hw NXP Semiconductors, tza3015hw Datasheet - Page 20

• Manufacturer Part Number: tza3015hw
• Description: 30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
All parts of the PLL are internal; no external components
are required. This allows for easy application.
Programming the clock synthesizer involves four dividers:
This is essentially the same as for the DCR.
The first step is to determine in which octave the desired
bit rate fits, see Tables 4 and 5 and Fig.7. Figure 7 shows
the position of the most commonly used line rates in
relation to the defined octaves of the TZA3015HW.
Table 5 clarifies the octave definitions; this yields the value
for the octave divider M. The value for R is determined by
the reference frequency and the received bit rate (see
Section “Reference clock programming”).
Prescaler output
The prescaler output TXPRSCL(Q) is the VCO frequency
of the synthesizer divided by the main division factor N.
If the synthesizer is in-lock, the frequency is equal to the
reference frequency at CREF(Q) divided by R. It can be
used as an accurate reference for another PLL. If needed,
the polarity of the prescaler outputs can be inverted by bit
TXPRSCLINV of register TXMFOUTC (F2h).
If no prescaler information is desired, the output can be
disabled by bit TXPRSCLEN of the same register. Apart
from these settings, the signal amplitude can be set. This
parameter follows the settings of the LVDS outputs. For
programming details, see Section “LVDS outputs”.
Loss of lock
During operating, the loss of lock output pin LOL should be
LOW which means that the clock synthesizer is in-lock and
the output frequency corresponds to the programmed
value. If pin LOL goes HIGH, phase and/or frequency lock
is lost and the output frequency may deviate from the
programmed value. The LOL condition is also available in
the registers INTERRUPT (00h) and STATUS (01h).
On demand (interrupt is default masked), it generates an
interrupt signal at pin INT.
M
The multiplexer comprises a high-speed input register, a
4-stage First In First Out (FIFO) elastic buffer, a parity
check circuit and the actual multiplexing tree.
2003 Dec 16
ULTIPLEXER
Reference divider R
Main divider N
Fractional divider K
Octave divider M.
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
20
Parallel bus clocking schemes
The TZA3015HW supports both co-directional and
contra-directional clocking schemes for the parallel data
bus. The clocking application can be selected by pin
CLKDIR or by the bit CLKDIR of register MUXCON0 (F1h).
Co-directional clocking is default.
Table 10 Truth table for clocking scheme
In the co-directional clocking mode, the parallel clock
signal is applied to pins TXPC(Q). The parallel clock signal
is generated in the data processing device (e.g. a framer).
The co-directional application is depicted in Fig.15. The
data processing device may be clocked by an external
crystal or by the parallel clock output TXPCO(Q) of the
TZA3015HW. This clock output is internally derived from
the synthesizer. If the parallel clock output TXPCO(Q) is
not required, it can be disabled in order to save dissipation.
This is done by programming bit TXPCOEN of register
TXMFOUTC (F2h).
In a contra-directional clock application, no clock is
provided on pin TXPC (see Fig.16). The clock that
samples the input data on the parallel bus, is an internal
clock derived from signal TXPCO. In this application, the
part providing the parallel data has to be clocked with the
clock signal TXPCO(Q). In order to alleviate timing
problems, the phase of clock TXPCO(Q), with respect to
the internal clock, can be shifted in 90 steps. Bit
TXPCOINV (180 ) of register TXMFOUTC (F2h) together
with bit TXPOPHASE (90 ) of register MUXCON0 (F1h)
sets the phase shift (see Table 11).
Table 11 Truth table for bits TXPCINV and TXPOPHASE
PIN CLKDIR BIT CLKDIR
TXPCOINV
HIGH
LOW
0
0
1
1
0
1
TXPOPHASE
0
1
0
1
contra-directional clocking
co-directional clocking
Preliminary specification
TZA3015HW
APPLICATION
PHASE SHIFT
180
270
90
0