tza3015hw NXP Semiconductors, tza3015hw Datasheet - Page 16

• Manufacturer Part Number: tza3015hw
• Description: 30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
from these settings, the signal amplitude can be set. This
parameter follows the settings of the LVDS outputs. For
programming details, see Section “LVDS outputs”.
FWD programming
The default width of the window for frequency acquisition
is 1000 ppm around the required bit rate. This window size
can be changed between 4000 and 250 ppm by bits
WINSIZE[2:0] of register DCRCON (C6h). This allows for
loose or tight coupling of the VCO to the applied reference
clock. Another feature is to define a window width of
0 ppm, by means of pin WINSIZE, see Table 8. This
effectively removes the dead zone from the FWD,
rendering the FWD into a classical PLL.
The VCO will be directly locked to the reference signal
instead of the incoming bit stream. Apart from pin
WINSIZE, this mode can be invoked by bits I2CWINSIZE
and WINSIZE of register DCRCON(C6h).
Table 8 Truth table for pin WINSIZE
Accurate clock generation during loss of signal
A zero window size is especially interesting in the absence
of input data, since the frequency of the ‘recovered clock’
will be equal to the programmed line clock rate.
Bit AUTOWIN of register DCRCON (C6h) (see Table 9)
makes the window size dependent on the LOS status of
the limiter. If the optical input signal is lost, the FWD
automatically selects the 0 ppm window size; i.e. a direct
lock to the reference frequency. This results in a stable and
defined output clock during LOS situations, while
automatically reverting back to normal DCR operating
when the input signal returns.
The accuracy of the reference frequency needs to be
better than 20 ppm if the application has to comply with
ITU-T recommendations.
Table 9 Truth table for bit AUTOWIN
2003 Dec 16
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
AUTOWIN
WINSIZE
HIGH
LOW
0
1
FWD user defined
FWD dependent on LOS
FREQUENCY WINDOW (ppm)
FREQUENCY WINDOW
1000
0
16
INWINDOW output
The status of the FWD circuit is reflected in the state of pin
INWINDOW; HIGH for an ‘in window’ situation and LOW
whenever the VCO is outside the defined frequency
window. Due to the fact that the device enters the
frequency acquisition mode when out of window is
detected, the INWINDOW pin will have an intermittent
value when the input signal is not within the defined
window boundary.
D
The demultiplexer converts the serial input bit stream to a
parallel format. The output data is available on a 4-bit
LVDS-bus, thus reducing the data frequency by a factor
four. Apart from the de-serializing function, the
demultiplexer comprises a parity calculator and a frame
header detection circuit.
The calculated parity (even) is available at output pins
RXPAR(Q), whereas occurrence of the frame header
pattern in the data stream results in a one clock cycle
(parallel clock output) wide pulse on output pins RXFP(Q).
If pin ENBA is HIGH, automatic byte (word) alignment
takes place, formatting the parallel output to logical
nibbles. Apart from pin ENBA, this mode can be invoked
by bits I2CENBA and ENBA of register DMXCON (B8h).
To support most commonly used transmission protocols,
the frame header pattern can be programmed to any 32-bit
pattern (see Section “Frame detection”).
If required, the demultiplexer output can be forced into a
fixed logic state by bit DMXMUTE of register DMXCON
(B8h).
The highest supported parallel bus speed is 800 Mbit/s.
Frame detection
Byte alignment is enabled if the enable byte alignment
input (pin ENBA) is forced HIGH. Whenever a 32-bit
sequence matches the programmed header pattern, the
incoming data is formatted into logical bytes (being output
as nibbles) and a frame pulse is generated on differential
output pins RXFP(Q). Any header pattern can be
programmed through registers HEADER3 to HEADER0
(B0h to B3h). It is possible to enter a ‘don’t care’ for any bit
position, e.g. to program a header pattern that is much
shorter than 32 bits or to program a pattern with a gap in it.
EMULTIPLEXER
Preliminary specification
TZA3015HW