tza3015hw NXP Semiconductors, tza3015hw Datasheet - Page 23

• Manufacturer Part Number: tza3015hw
• Description: 30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Parity checking
In order to check the integrity of the data provided on the
parallel input bus, a parity checking function has been
implemented in the TZA3015HW. The calculated parity,
based on the data currently on the bus, is compared to the
expected parity provided at pins TXPAR(Q). If these do not
match, i.e. a parity error has occurred, the output pins
TXPARERR(Q) are HIGH during the next parallel bus
clock (TXPC) period.
Odd or even parity checking can be selected by pin
PAREVEN or by bit TXPAREVEN of register MUXCON1
(F0h). I
setting bit I2CTXPAREVEN of register MUXCON1 (F0h).
A HIGH-level on pin PAREVEN corresponds with even
parity (default for bit TXPAREVEN), see Table 16.
Table 16 Truth table for parity setting
Jitter performance
The clock synthesizer has been optimized for lowest jitter
generation and the data and clock recovery has been
optimized for the best jitter tolerance. For all SDH/SONET
line rates, the jitter tolerance and the jitter generation is
compliant with ITU-T standard G.958, provided the
reference clock is clean enough. For optimum jitter
generation, the single-sideband phase noise of the
reference frequency should be less than 140 dBc/Hz, for
frequencies greater than 12 kHz from the carrier. If the
reference divider R is used, this requirement elevates with
approximately 20
Configuring the main functionality
O
The TZA3015HW can be configured in several operating
modes. It can be configured as:
The transceiver configuration is the default operating
mode. The transmitter and receiver part can be enabled
2003 Dec 16
PERATING MODES
Transceiver
Transmitter
Receiver
Transponder with clean-up PLL.
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
PIN PAREVEN
HIGH
2
LOW
C-bus control of the parity type is enabled by
log R.
BIT TXPAREVEN
0
1
PARITY TYPE
even
odd
23
independently. This saves power when only one half of the
functionality is needed. The TZA3015HW can also be
configured as a clean-up PLL. This is described in the
Section “Loop modes”. The operating modes can be
selected with pins ENRX and ENTX, these pins enable the
receiver and the transmitter. This also offers the possibility
to power-down the complete IC. Operating (or enable)
modes are listed in Table 17.
Table 17 Truth table for the operating modes
L
The TZA3015HW supports four loop modes:
Selecting the loop modes
The required loop mode can be selected either by
pins LM0, LM1 and LM2 or by I
The pin settings for the loop mode selection can be seen
in Table 18.
Table 18 Loop mode selection; note 1
Note
1. The loop mode can be also programmed by setting
OOP MODES
HIGH
HIGH
HIGH
LOW
LOW
LOW
LM2
Line loop back
Diagnostic loop back
Serial loop timing
Clean-up loop back.
ENRX
HIGH
HIGH
LOW
LOW
bits LM[2:0] in register LOOPMODE (A3h).
HIGH
HIGH
HIGH
LOW
LOW
LOW
LM1
ENTX
HIGH
HIGH
LOW
LOW
HIGH line loop back
HIGH serial loop timing
HIGH normal
LOW
LOW
LOW
LM0
power-down
transmitter
receiver
transceiver (or transponder)
normal
diagnostic loop back
clean-up loop back
OPERATING MODE
2
C-bus control.
Preliminary specification
TZA3015HW
MODE