tza3015hw NXP Semiconductors, tza3015hw Datasheet - Page 28

• Manufacturer Part Number: tza3015hw
• Description: 30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
connectivity problems with other ICs are avoided. Unused
outputs can be disabled.
These options can be programmed in registers
TXRFOUTC1 (F3h) and TXRFOUTC0 (F4h). The
following RF outputs are available:
The RF CML data and clock outputs have an adjustable
signal amplitude between 70 and 1100 mV (p-p)
single-ended in 16 steps. The amplitude can be
programmed by setting bits RFS[3:0] of register
TXRFOUTC0 (F4h). The default amplitude is
300 mV (p-p) single-ended.
The clock and data outputs can be swapped by
programming bit TXSDSCSWAP of register TXRFOUTC1
(F3h). Allowing full flexibility in the PCB design.
The data and clock outputs can be DC- or AC-coupled to
the laser driver. The TZA3015HW serial RF outputs can be
adapted to this for optimal connectivity by appropriately
setting bit RFOUTTERMAC of register TXRFOUTC0
(F4h). DC termination is default.
Serial clock output
The polarity of the serial clock output TXSC(Q) can be
programmed by bit TXSCINV of register TXRFOUTC1
(F3h). The serial clock output can be disabled by setting
pin ENTXSC or by programming bit TXSCEN of register
TXRFOUTC1 (F3h) (see Table 20). This saves power
dissipation in applications where the serial clock is not
needed
Table 20 Truth table for serial clock enable
In order to control the enabling of the serial clock output by
the I
(F3h) must be programmed.
Serial data output
The polarity of the serial data output TXSD(Q) can be
programmed by bit TXSDINV of register TXRFOUTC1
(F3h). The data output can be disabled by programming bit
TXSDEN of register TXRFOUTC1 (F3h).
2003 Dec 16
PIN ENTXSC
Serial data output; pins TXSD(Q)
Serial clock output; pins TXSC(Q).
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
2
C-bus, bit I2CTXSCEN of register TXRFOUTC1
HIGH
LOW
BIT ENTXSC
0
1
disabled
enabled
SERIAL CLOCK
28
R
The reference clock CREF(Q) input is shown in Fig.36
RF
The serial data inputs are pins RXSD(Q). These pins are
differential CML type serial RF data inputs. There are no
special settings for these inputs.
CMOS
The CMOS outputs are all used as logic outputs to indicate
the status of the TZA3015HW.
A LOW state equals the ground potential and a HIGH state
equals the supply voltage. The INT output can be
configured as CMOS output or as open-drain output (see
Sections “Open-drain output” and “Interrupt generation”).
The output is configured as open-drain output by default.
CMOS
The CMOS inputs are all used as logic inputs to configure
the TZA3015HW:
EFERENCE CLOCK INPUT
Loss of signal output; pin LOS
Frequency window detector output; pin INWINDOW
Interrupt output; pin INT
Loss of lock output; pin LOL
FIFO overflow alarm output; pin OVERFLOW.
User interface selection input; pin UI
Data rate selection inputs; pins DR0 to DR2
Loop mode selection inputs; pins LM0 to LM2
Enable receiver input; pin ENRX
Enable transmitter input; pin ENTX
Wide and narrow frequency detect window selection
input; pin WINSIZE
Enable low LVDS swing output input; pin LOWSWING
Reference frequency selection inputs; pins FREF0 and
FREF1
Enable byte alignment input; pin ENBA
FIFO reset input; pin FIFORESET
Odd or even parity check input; pin PAREVEN
Co-directional or contra-directional clocking selection
input; pin CLKDIR
Enable serial clock input; pin ENTXSC.
INPUT
OUTPUTS
INPUTS
Preliminary specification
TZA3015HW