tza3015hw NXP Semiconductors, tza3015hw Datasheet - Page 29

• Manufacturer Part Number: tza3015hw
• Description: 30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The CMOS inputs have an internal pull-up resistance; if
the input is left open, a logic HIGH state will be forced
internally. In the pre-programmed mode (UI = LOW), pins
DR0 to 2 act as regular CMOS inputs. In the I
(UI = HIGH), pins SCL and SDA comply with the I
interface standard.
O
The TZA3015HW contains one open-drain interrupt output
pin INT. The output type of the interrupt controller can be
configured by programming bit INTOUT of register
INTCONF (A5h). The output can be configured as a
push-pull CMOS output or as an open-drain output. For the
open-drain configuration an external pull-up resistor of
3.3 k is recommended. The polarity can be set by
programming bit INTPOL of register INTCONF (A5h).
I
The TZA3015HW features a fully configurable interrupt
generator. An interrupt signal can be generated in the
following events:
The aforementioned events generate flags which can be
read in register STATUS (01h). Each of these flags will
generate an interrupt in the INTERRUPT register (00h).
If programmed so in the register INTMASK (A0h) the
INTERRUPT register bit(s) will generate an interrupt on
pin INT. In this mask register each interrupt bit can be
masked by writing a logic 0 in the corresponding bit
position.
The STATUS register shows the present status of the
receiver. The INTERRUPT register shows the history of
the interrupts and is not affected by the INTMASK register.
Bit INTOUT of register INTCONF (A5h) determines the
output type of pin INT: standard CMOS output or
open-drain output. The latter is the default which provides
for multiple receivers sharing a common interrupt signal
wire with a 3.3 k pull-up resistor (INT is active LOW in
this case). The polarity can be set by programming bit
INTPOL of register INTCONF (A5h).
The interrupt and status register can be polled by an
I
register the interrupt register is reset by clearing the
2003 Dec 16
NTERRUPT GENERATION
2
C-bus read action. After the read action on the interrupt
PEN
Loss Of Signal (LOS)
INWINDOW
Temperature alarm
Loss Of Lock (LOL)
FIFO overflow or underflow.
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
-
DRAIN OUTPUT
2
C-bus mode
2
C-bus
29
interrupt bits where the ‘alarm’ is no longer present. If the
‘alarm’ is still set, the interrupt bit is not cleared after the
read action. If an interrupt bit remains set (and if it is not
masked) the INT pin will keep its interrupt condition active;
it will not generate a pulse nor a spike. The I
register is not reset since it always shows the present
status of the receiver. It is important to note that the three
reserved bits of the STATUS and INTERRUPT registers
can take any value and that they can change during
operating. These bits can not be used to obtain information
on the status of the IC.
Power supply connections
Four separate supply domains (V
V
blocks. Each supply domain should be connected to a
common V
should be powered synchronously.
All supply pins, including the exposed die pad, must be
connected. The die pad should be connected with the
lowest inductance possible. Since the die pad is also used
as the main ground return of the chip, the connection
should have a low DC impedance as well. The voltage
supply levels should be in accordance with the values
specified in Chapter “Characteristics”.
All external components should be surface mounted
devices, preferably of size 0603 or smaller. The
components must be mounted as closely to the IC as
possible.
I
I
The I
ICs or modules. The two lines are a serial data line (SDA)
and a serial clock line (SCL). Data transfer may be initiated
only when the line is not busy.
S
Figure 22 shows the definition of the start and stop
conditions. Both data and clock lines remain HIGH when
the bus is not busy. A HIGH-to-LOW transition of the data
line, while the clock is HIGH is defined as the start
condition (S). A LOW-to-HIGH transition of the data line
while the clock is HIGH is defined as the stop condition (P).
2
2
CCA
C-BUS
C-bus characteristics
TART AND STOP CONDITIONS
) provide isolation between the various functional
2
C-bus is a 2-line communication between different
CC
via separate filters. All supply domains
Preliminary specification
DD
TZA3015HW
, V
CCD
, V
2
C-bus status
CCO
and