tmp89fm82t TOSHIBA Semiconductor CORPORATION, tmp89fm82t Datasheet - Page 328

• Manufacturer Part Number: tmp89fm82t
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

19.5
Three-phase PWM Output Unit
EMGCRB
EMGCRA
19.5.5
Protective Circuit Registers
7 to 4
3, 2
EMGREL
(0x0EDF)
7
6
5
4
1
0
2
1
0
EMGREL
Note:Read-modify-write instructions, such as a bit manipulation instruction, cannot access the EMGREL register be-
cause this register is write only.
7 to 0
Functions of Protective Circuit Registers
RTPWM
EMGEN
EMGST
RTTM1
CNTST
CLCNT
CLMD
RTCL
CLEN
CLST
RTE
D7
7
EMG disable
EMGREL
D6
Return from overload protec-
tive state
Return by PWM sync
Return by timer sync
Overload protective state
Select output disabled phases
during overload protection
Stop counter during overload
protection
Enable/Disable overload pro-
tection
Overload protection sampling
time
EMG protective state
Return from EMG protective
state
Enable/Disable EMG protec-
tive circuit
6
EMG disable
D5
5
D4
4
The EMG protective circuit can be disabled from the enabled state by writing “0x5A“ and
“0xA5“ to this register in that order. After that, the EMGCRA<EMGEN> bit needs to be
cleared to disable EMG circuit..
When this bit is set to "1", the motor control circuit can return from overload protective state
in software (e.g., by writing to this register).
When this bit is set to "1," the motor control circuit can return from overload protective state
by PWM sync. If <RTCL> is set to "1", <RTCL> has priority.
When this bit is set to 1, the motor control circuit is returned from overload protective state
by Timer 1 sync. If <RTCL> is set to "1",< RTCL> has priority.
The status of overload protection can be known by reading this bit.
Select the phases to be disabled against output during overload protection. This facility
allows selecting to disable no phases, all phases, PWM phases, or all upper phases/all
lower phases.
Can stop the PWM counter during overload protection.
Enable or disable the overload protective function.
Set the length of time the overload protective input port is sampled.
The status of EMG protection can be known by reading this bit.
The motor control circuit is returned from EMG protective state by setting this bit to “1” .
When returning, set the MDOUT Register 11 to 0 bits to “0” . Then set this EMGCRA<RTE>
bit to “1” and set MDOUT output waveform. Then set up the MDCRA Register.
<PWMEN>etc.
The EMG protective circuit is activated by setting this bit to "1". This circuit initially is ena-
bled.
(To disable this circuit, make sure key code "0x5A" and "0xA5" are written to the EMGREL
Register beforehand.)
D3
3
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Can disable by writing 0x5A and then 0xA5.
D2
2
D1
1
D0
0
(Initial value: 0000 0000)
TMP89FM82T
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