tmp89fm82t TOSHIBA Semiconductor CORPORATION, tmp89fm82t Datasheet - Page 44

• Manufacturer Part Number: tmp89fm82t
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.3
System clock controller
RA000
2.3.6.2
and generated from the clock that is a quarter of the low-frequency clock (fs) in the SLOW1/2 or SLEEP0/1
mode. Therefore, the machine cycle time is 1/fcgck [s] in the NORMAL2 or IDLE2 mode and is 4/fs [s] in
the SLOW1/2 or SLEEP0/1 mode.
cannot be used as I/O ports in the dual-clock mode.)
in the dual-clock mode, allow the low-frequency clock to oscillate at the program.
(1)
(2)
(3)
The gear clock (fcgck) and the low-frequency clock (fs) are used for the operation in the dual-clock mode.
The main system clock (fm) is generated from the gear clock (fcgck) in the NORMAL2 or IDLE2 mode,
P02 (XTIN) and P03 (XTOUT) are used as the low-frequency clock oscillation circuit pins. (These pins
The operation of the TLCS-870/C1 Series becomes the single-clock mode after reset release. To operate it
Dual-clock mode
is released, the timing generator starts the clock supply to all the peripheral circuits and the NORMAL1
mode is restored.
set after the NORMAL mode is restored.
the operation returns normal after the interrupt processing is completed.
time base timer) is "0", the operation is restarted by the instruction that follows the IDLE0 mode acti-
vation instruction.
using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs).
low-frequency clock (fs).
For operations of the peripheral circuits in the SLOW mode, refer to the section of each peripheral
circuit.
to NORMAL2.
peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs).
SLOW2 mode.
When the falling edge of the source clock selected at TBTCR<TBTCK> is detected, the IDLE0 mode
Note that the IDLE0 mode is activated and restarted, regardless of the setting of TBTCR<TBTEN>.
When the IDLE0 mode is activated with TBTCR<TBTEN> set at "1", the INTTBT interrupt latch is
When the IMF is "1" and the EF5 (the individual interrupt enable flag for the time base timer) is "1",
When the IMF is "0" or when the IMF is "1" and the EF5 (the individual interrupt enable flag for the
In this mode, the CPU core operates using the gear clock (fcgck), and the peripheral circuits operate
In this mode, the CPU core and the peripheral circuits operate using the clock that is a quarter of the
In the SLOW mode, some peripheral circuits become the same as the states when a reset is released.
Set SYSCR2<SYSCK> to switch the operation mode from NORMAL2 to SLOW2 or from SLOW2
In the SLOW2 mode, outputs of the prescaler and stages 1 to 8 of the divider stop.
In this mode, the high-frequency clock oscillation circuit stops operation and the CPU core and the
This mode requires less power to operate the high-frequency clock oscillation circuit than in the
NORMAL2 mode
SLOW2 mode
SLOW1 mode
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TMP89FM82T