dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 132

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 8-3:
REGISTER 8-4:
DS70292C-page 130
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the
Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the con-
R/W-0
R/W-0
R/W-0
R/W-0
contents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
tents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
STA<15:0>: Primary DMA RAM Start Address bits (source or destination)
STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)
R/W-0
R/W-0
R/W-0
R/W-0
DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A
DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Preliminary
STB<15:8>
STA<15:8>
STA<7:0>
STB<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
© 2009 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
(1)
(1)
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0