dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 77

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

6.0
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
FIGURE 6-1:
© 2009 Microchip Technology Inc.
Note:
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
RESETS
This data sheet summarizes the features
of
dsPIC33FJ64GPX02/X04
dsPIC33FJ128GPX02/X04
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “dsPIC33F Family Reference Manual”,
“Section 8. Reset” (DS70192), which is
available from the Microchip website
(www.microchip.com).
MCLR
V
DD
the
Uninitialized W Register
Configuration Mismatch
RESET SYSTEM BLOCK DIAGRAM
Regulator
RESET Instruction
Internal
Sleep or Idle
dsPIC33FJ32GP302/304,
Module
Illegal Opcode
WDT
Trap Conflict
V
Detect
families
DD
Glitch Filter
Rise
and
Preliminary
BOR
POR
of
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of reset will make the SYSRST sig-
nal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1).
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Refer to the specific peripheral section or
Section 3.0 “CPU” of this manual for
register Reset states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
SYSRST
DS70292C-page 75