dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 90

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 7-1:
DS70292C-page 88
bit 15
bit 7
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
bit 7-5
Note 1: For complete register details, see Register 3-1: “SR: CPU STATUS REGISTER”.
R/W-0
IPL2
R-0
OA
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
(2)
(3)
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
R/W-0
IPL1
R-0
OB
SR: CPU STATUS REGISTER
(2)
(3)
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
R/W-0
IPL0
R/C-0
SA
(2)
(3)
R/C-0
R-0
RA
SB
Preliminary
(1)
-n = Value at POR
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
R/W-0
OAB
R-0
N
(2)
R/W-0
R/C-0
SAB
OV
© 2009 Microchip Technology Inc.
R/W-0
R -0
DA
Z
R/W-0
R/W-0
DC
C
bit 8
bit 0