dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 141

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

9.1.4
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 9-2.
The output of the primary oscillator or FRC, denoted as
‘F
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor
‘N2.’ This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(F
generates device operating speeds of 6.25-40 MIPS.
FIGURE 9-2:
© 2009 Microchip Technology Inc.
Source (Crystal, External Clock
IN
OSC
or Internal RC)
’, is divided down by a prescale factor (N1) of 2, 3,
Note 1: This frequency range must be satisfied at all times.
) is in the range of 12.5 MHz to 80 MHz, which
factor
PLL CONFIGURATION
‘N1’
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 AND dsPIC33FJ128GPX02/
X04 PLL BLOCK DIAGRAM
is
selected
Divide by
PLLPRE
2-33
N1
using
0.8-8.0 MHz
Here
Preliminary
the
(1)
X
For a primary oscillator or FRC oscillator, output ‘F
the PLL output ‘F
EQUATION 9-2:
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL.
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a
• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
• If PLLPOST<1:0> = 0, then N2 = 2. This provides
EQUATION 9-3:
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
VCO output of 5 x 32 = 160 MHz, which is within
the 100-200 MHz ranged needed.
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
Divide by
PLLDIV
F
2-513
VCO
CY
M
=
100-200 MHz
F
OSC
2
F
Here
OSC
F
VCO
=
OSC
(1)
= F
1
2
’ is given by:
(
IN
PLLPOST
F
XT WITH PLL MODE
EXAMPLE
Divide by
10000000 • 32
•
OSC
2, 4, 8
(
N2
N1 • N2
2 • 2
CALCULATION
M
12.5-80 MHz
)
DS70292C-page 139
)
Here
=
40 MIPS
(1)
F
OSC
IN
’,