dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 91

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 7-2:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
0’ = Bit is cleared
bit 3
Note 1: For complete register details, see Register 3-2: “CORCON: CORE CONTROL REGISTER”.
R/W-0
SATA
U-0
—
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
R/W-0
SATB
U-0
—
CORCON: CORE CONTROL REGISTER
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
SATDW
R/W-1
U-0
—
ACCSAT
R/W-0
R/W-0
US
Preliminary
-n = Value at POR
U = Unimplemented bit, read as ‘0’
(2)
IPL3
R/W-0
R/C-0
EDT
(2)
(1)
R/W-0
PSV
R-0
‘1’ = Bit is set
DL<2:0>
R/W-0
RND
R-0
DS70292C-page 89
R/W-0
R-0
IF
bit 8
bit 0