dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 18

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

TABLE 1-1:
DS70292C-page 16
SCL1
SDA1
ASCL1
ASDA1
TMS
TCK
TDI
TDO
C1RX
C1TX
RTCC
CV
C1IN-
C1IN+
C1OUT
C2IN-
C2IN+
C2OUT
PMA0
PMA1
PMA2 -PMPA10
PMBE
PMCS1
PMD0-PMPD7
PMRD
PMWR
DAC1RN
DAC1RP
DAC1RM
DAC1LN
DAC1LP
DAC1LM
COFS
CSCK
CSDI
CSDO
PGWD1
PGEC1
PGWD2
PGEC2
PGWD3
PGEC3
MCLR
AV
Legend: CMOS = CMOS compatible input or output
DD
REF
Pin Name
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
PINOUT I/O DESCRIPTIONS (CONTINUED)
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/P
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P
I
I
I
I
I
I
I
I
I
I
I
I
TTL/ST
TTL/ST
TTL/ST
Buffer
Type
ANA
ANA
ANA
ANA
ANA
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P
PPS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
Real-Time Clock Alarm Output.
Comparator Voltage Reference Output.
Comparator 1 Negative Input.
Comparator 1 Positive Input.
Comparator 1 Output.
Comparator 2 Negative Input.
Comparator 2 Positive Input.
Comparator 2 Output.
Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and
Output (Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and
Output (Master modes).
Parallel Master Port Address (Demultiplexed Master Modes).
Parallel Master Port Byte Enable Strobe.
Parallel Master Port Chip Select 1 Strobe.
Parallel Master Port Data (Demultiplexed Master mode) or Address/
Data (Multiplexed Master modes).
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.
DAC1 Right Channel Negative Output.
DAC1 Right Channel Positive Output.
DAC1 Right Channel Middle Point Value (typically 1.65V).
DAC1 Left Channel Negative Output.
DAC1 Left Channel Positive Output.
DAC1 Left Channel Middle Point Value (typically 1.65V).
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin
Data Converter Interface serial data output pin.
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
Positive supply for analog modules. This pin must be connected at all
times.
Preliminary
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
Description
© 2009 Microchip Technology Inc.
P = Power
I = Input