dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 380

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

ECAN Registers
ECAN Transmit/Receive Error Count Register (CiEC) ..... 227
ECAN TX/RX Buffer m Control Register (CiTRmnCON) .. 238
Electrical Characteristics................................................... 317
Enhanced CAN Module..................................................... 217
Equations
Errata .................................................................................. 12
F
Flash Program Memory....................................................... 69
DS70292C-page 378
CiFEN1 register ........................................................ 229
CiFIFO register ......................................................... 224
CiFMSKSEL1 register ............................................... 233
CiFMSKSEL2 register ............................................... 234
CiINTE register ......................................................... 226
CiINTF register.......................................................... 225
CiRXFnEID register .................................................. 233
CiRXFnSID register .................................................. 232
CiRXFUL1 register .................................................... 236
CiRXFUL2 register .................................................... 236
CiRXMnEID register.................................................. 235
CiRXMnSID register.................................................. 235
CiRXOVF1 register ................................................... 237
CiRXOVF2 register ................................................... 237
CiTRmnCON register ................................................ 238
CiVEC register .......................................................... 222
ECAN1 Register Map (C1CTRL1.WIN = 0 or 1) ......... 51
ECAN1 Register Map (C1CTRL1.WIN = 0) ................ 51
ECAN1 Register Map (C1CTRL1.WIN = 1) ................ 52
Frame Types ............................................................. 217
Modes of Operation .................................................. 219
Overview ................................................................... 217
Acceptance Filter Enable Register (CiFEN1)............ 229
Acceptance Filter Extended Identifier Register n (CiRXF-
Acceptance Filter Mask Extended Identifier Register n
Acceptance Filter Mask Standard Identifier Register n
Acceptance Filter Standard Identifier Register n (CiRXF-
Baud Rate Configuration Register 1 (CiCFG1) ......... 227
Baud Rate Configuration Register 2 (CiCFG2) ......... 228
Control Register 1 (CiCTRL1) ................................... 220
Control Register 2 (CiCTRL2) ................................... 221
FIFO Control Register (CiFCTRL) ............................ 223
FIFO Status Register (CiFIFO) ................................. 224
Filter 0-3 Buffer Pointer Register (CiBUFPNT1) ....... 229
Filter 12-15 Buffer Pointer Register (CiBUFPNT4) ... 231
Filter 15-8 Mask Selection Register (CiFMSKSEL2). 234
Filter 4-7 Buffer Pointer Register (CiBUFPNT2) ....... 230
Filter 7-0 Mask Selection Register (CiFMSKSEL1)... 233
Filter 8-11 Buffer Pointer Register (CiBUFPNT3) ..... 230
Interrupt Code Register (CiVEC) .............................. 222
Interrupt Enable Register (CiINTE) ........................... 226
Interrupt Flag Register (CiINTF) ............................... 225
Receive Buffer Full Register 1 (CiRXFUL1).............. 236
Receive Buffer Full Register 2 (CiRXFUL2).............. 236
Receive Buffer Overflow Register 2 (CiRXOVF2)..... 237
Receive Overflow Register (CiRXOVF1) .................. 237
AC ............................................................................. 326
Device Operating Frequency .................................... 138
Control Registers ........................................................ 70
Operations .................................................................. 70
Programming Algorithm .............................................. 73
RTSP Operation.......................................................... 70
Table Instructions........................................................ 69
nEID)................................................................. 233
(CiRXMnEID) .................................................... 235
(CiRXMnSID) .................................................... 235
nSID)................................................................. 232
Preliminary
Flexible Configuration ....................................................... 295
I
I/O Ports............................................................................ 155
I
In-Circuit Debugger........................................................... 301
In-Circuit Emulation .......................................................... 295
In-Circuit Serial Programming (ICSP)....................... 295, 301
Input Capture .................................................................... 191
Input Change Notification ................................................. 156
Instruction Addressing Modes ............................................ 60
Instruction Set
Instruction-Based Power-Saving Modes........................... 149
Internal RC Oscillator
Internet Address ............................................................... 381
Interrupt Control and Status Registers ............................... 87
Interrupt Setup Procedures............................................... 124
Interrupt Vector Table (IVT) ................................................ 83
Interrupts Coincident with Power Save Instructions ......... 150
J
JTAG Boundary Scan Interface ........................................ 295
JTAG Interface.................................................................. 301
M
Memory Organization ......................................................... 35
Microchip Internet Web Site.............................................. 381
Modes of Operation
Modulo Addressing ............................................................. 62
MPLAB ASM30 Assembler, Linker, Librarian ................... 314
MPLAB ICD 2 In-Circuit Debugger ................................... 315
MPLAB ICE 2000 High-Performance Universal In-Circuit Em-
2
C
Parallel I/O (PIO) ...................................................... 155
Write/Read Timing .................................................... 156
Operating Modes ...................................................... 203
Registers .................................................................. 203
Registers .................................................................. 192
File Register Instructions ............................................ 60
Fundamental Modes Supported ................................. 61
MAC Instructions ........................................................ 61
MCU Instructions ........................................................ 60
Move and Accumulator Instructions............................ 61
Other Instructions ....................................................... 61
Overview................................................................... 308
Summary .................................................................. 305
Idle ............................................................................ 150
Sleep ........................................................................ 149
Use with WDT........................................................... 300
IECx ............................................................................ 87
IFSx ............................................................................ 87
INTCON1 .................................................................... 87
INTCON2 .................................................................... 87
IPCx ............................................................................ 87
Initialization ............................................................... 124
Interrupt Disable ....................................................... 124
Interrupt Service Routine .......................................... 124
Trap Service Routine ................................................ 124
Disable...................................................................... 219
Initialization ............................................................... 219
Listen All Messages.................................................. 219
Listen Only................................................................ 219
Loopback .................................................................. 219
Normal Operation ..................................................... 219
Applicability................................................................. 63
Operation Example ..................................................... 62
Start and End Address ............................................... 62
W Address Register Selection .................................... 62
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